Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Mun Kee Choi

Kyung Soo Kim

Jun Kyun Choi

Hyup Jong Kim

Young Soo Shin

Kyeong Soo Kim

Tae Soo Jeong

Myeong Suk Kim

Tae Woon Kang

Suk Chun Song

To provide a high speed traffic statictics processing apparatus using memory so that a statistical processing for an enormous amount of measured data can be executed in real time by manipulating partially the measured data and storing the partially manipulated measured data using memory and a simple circuit, not transferring the enormous amount of measured data directly to a statistical processor, the present invention comprises a measurement traffic extractor for discriminating the measured traffics from other traffics and extracting the measured traffics, a traffic manipulator for manipulating the extracted traffics, a traffic statistical processor for executing the statistical processing of the manipulated traffic, a traffic dispaly for displaying the data which traffics are processed for and an application processor for requesting for the traffic measurement and controlling their overall operation.

Traffic statistics processing apparatus using memory to increase speed

An ATM multiplexing system comprising a plurality of ATM cell input circuits, each of which stores a cell stream incoming from a corresponding input stage and absorbs and removes instantaneous displacement of the incoming cells, a priority encoder for receiving simultaneously FIFO storage level information from the ATM cell input circuits and determining a priority for processing first an input stage with the largest number of stored cells, the FIFO storage level information including the number of the cells stored in the ATM cell input circuits, a link table processing circuit for receiving output headers from the priority encoder and input port numbers corresponding to the received headers and outputting changed headers corresponding to the received headers, an ATM cell output circuit for receiving the changed headers and link information from the link table processing circuit, determining a cell transmission order according to a service priority and performing a header assembling function for perfect cell production, a cell transmission controller for transmitting output headers from the ATM cell output circuit and the corresponding payloads and controlling the above-mentioned components, and a clock signal control circuit for generating a clock signal to control timing of the above-mentioned components.

ATM multiplexing system

A high speed ATM cell synchronizing switching apparatus is disclosed, and the apparatus includes: a plurality of ATM cell inputting circuits 1 for receiving optical ATM signals; a routing control circuit 2 for receiving address information; a cell gate circuit 3 for transmitting the inputted cells synchronously; a switching information tabling circuit 4 for switching the switching information; and a switching matrix circuit 5 for receiving and outputting the switching control information and the cell data information.

High speed ATM cell synchronizing switching apparatus

Growing community of inventors

Daejeon, South Korea

Mun Kee Choi