Samsung Electronics Co., Ltd.

Mun-Hyeon Kim

Keun-Hwi Cho

Shigenobu Maeda

Dong-won Kim

Sung-il Park

Dae-Won Ha

Myung-gil Kang

Chang-woo Noh

Byoung-Hak Hong

Woong-Gi Kim

Toshinori Fukai

Sue-Hye Park

Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.

Semiconductor devices and inverter having the same

Provided is a semiconductor device to which a pattern structure for performance improvement is applied. The semiconductor device includes first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween, a first normal gate formed on the first active region to extend in a second direction crossing the first direction, a first dummy gate having a portion overlapping with one end of the isolation layer and the other portion overlapping with the first active region and spaced apart from the first normal gate in the first direction, a second dummy gate having a portion overlapping with the other end of the isolation layer and the other portion overlapping with the second active region, a first normal source/drain contact formed on a source/drain region between the first normal gate and the first dummy gate, and a dummy contact formed on the isolation layer so as not to overlap with the first and second dummy gates and having a different size from the first normal source/drain contact.

Semiconductor device

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Seoul, South Korea

Mun-Hyeon Kim