Agate Logic, Inc.

Cswitch Corporation

Mukunda Krishnappa

Dana How

Pohrong Rita Chu

Jason Golbus

Robert K Yu

Suresh Subramaniam

Dave Trossen

Kevin James

Malcolm J Wing

Godfrey P D'Souza

Jay B Patel

Colin Neal Murphy

Douglas A Laird

Ivo J Dobbelaere

Jack Liu

Suresh Subramanian

A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

Memory controller for heterogeneous configurable integrated circuit

Memory controller for heterogeneous configurable integrated circuits

A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).

Reconfigurable content-addressable memory

A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.

Heterogeneous configurable integrated circuit

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Cupertino, CA, United States of America

Mukunda Krishnappa