Microsoft Technology Licensing, LLC

Intel Corporation

Mukund Ramakrishna

Dimitrios Kaseridis

Shadi T Khasawneh

Atsuo Kuwahara

Eugene Gorbatov

Russell Jerome Fenger

Rajshree Chabukswar

Ahmad A Samih

Monica Gupta

Muhammad Abozaed

Vijay Dhanraj

Guruprasad Settuvalli

Christine M Lin

The described technology provides a method including receiving a request for allocating an incoming cacheline to one of a plurality of SFT entries in a snoop filter (SFT), performing a tag lookup function for a tag of the incoming cacheline in the SFT, in response to determining that the incoming cacheline is not part of an existing sector of any of the plurality of SFT entries, finding one or more candidate SFT entries, wherein the candidate SFT entries can be converted to an aggregated entry, selecting one of the candidate SFT entries, and allocating the incoming cacheline to the selected SFT entry.

Cache coherence using dynamic coarse-grained tracking

Memory controllers and related methods for implementing an address-based dynamic page close policy are described. An example method includes using a first tracker, having entries indexed by a hash of system memory addresses for a physical memory region, tracking page hits associated with the physical memory region to develop a historical record of page hits to the physical memory region. The method further includes using a second tracker, having entries indexed by a hash of system memory addresses for the physical memory region, tracking page hits to the physical memory region to develop a current record of page hits to the physical memory region. The method further includes predicting whether to close a page or keep the page open based on a comparison of the historical record of page hits to the physical memory region with the current record of page hits to the physical memory region.

Memory controller and related methods for implementing an address-based dynamic page close policy

The described technology provides a method including determining a cacheline sector associated with a snoop filter (SFT) having a plurality of SFT entries, determining a number of cachelines in the identified cacheline sector that are cached by one or more agents, and determining, based on the number of cachelines in the identified cacheline sector that are cached by one or more agents, a number of bits in a bit vector (BV) of one or more of the plurality of SFT entries, wherein the number of bits is required to track the one or more agents.

Cache coherence using adaptive coherency tracking based on cacheline size and cacheline sector size

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Operating system assisted prioritized thread execution

Disclosed embodiments relate to enhanced auto-precharge memory scheduling. In one example, a system includes a memory having a matrix of storage cells, which, responsive to a row address strobe (RAS) signal, activates a given row, responsive to a column address strobe (CAS) signal, selects storage cells in the given row, and, responsive to a combined auto-precharge (AP) and CAS signal, accesses, then closes the given row. A memory controller selects a memory request from a memory request queue, generates the RAS signal to activate a row, when another memory request to the row is enqueued, generates the CAS signal to select a storage cell, when another memory request to a same bank but a different row is enqueued, generates the combined AP and CAS signal, and, when no memory request to the same bank is enqueued, generates the CAS signal only, allowing a close timer to close the row.

Enhanced auto-precharge memory scheduling policy

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Austin, TX, United States of America

Mukund Ramakrishna