Qualcomm Incorporated

Mukul Gupta

Xiangdong Chen

Hyeokjin Lim

Venugopal Boynapalli

Satyanarayana Sahu

Ohsang Kwon

Foua Vang

Mickael Malabry

Kern Rim

Stanley Seungchul Song

Haining S Yang

Pratyush Kamal

Raymond George Stephany

Radhika Vinayak Guttal

Chih-lung Kao

Hananel Kang

Jingwei Zhang

Hyeokjin Bruce Lim

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mlayer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mlayer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mlayer interconnects are parallel. The MOS device further includes a first Mlayer interconnect extending in a second direction orthogonal to the first direction. The first Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The MOS device further includes a second Mlayer interconnect extending in the second direction. The second Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The second Mlayer interconnect is parallel to the first Mlayer interconnect.

Multiple via structure for high performance standard cells

Metal oxide semiconductor device of an integrated circuit

A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

Standard cell architecture with M1 layer unidirectional routing

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Hybrid coloring methodology for multi-pattern technology

A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches

A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

Cross-couple in multi-height sequential cells for uni-directional M1

A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.

Source separated cell

An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

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San Diego, CA, United States of America

Mukul Gupta