Quicklogic Corporation

Mukesh T Lulla

William D Cox

Andrew K Chan

David D Eaton

Drazen Borkovic

Kevin K Yee

Brian D Small

Venkatesh R Nathamuni

Charles C Tralka

Eric E Lehmann

Roger Ang

Ker-Ching Liu

Atul Ahuja

A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.

Programmable device with an embedded portion for receiving a standard circuit design

A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.

Clock network for field programmable gate array

A sequence of antifuses to be programmed is determined by: determining whether a first antifuse of an unordered list of antifuses to be programmed could be programmed last without programming any antifuses which are not to be programmed, determining whether a second antifuse of the unordered list could be programmed last without programming any antifuses which are not be programmed, and determining whether the first and second antifuses could be programmed simultaneously without programming any antifuses which are not to be programmed. In this way, a programming set of antifuses which could be programmed simultaneously is determined. Once determined, the antifuses making up the programming set are added to the head of an ordered list and are removed from the unordered list. By repeatedly determining programming sets of antifuses and adding each successive set of antifuses to an ordered list of antifuses, an antifuse programming sequence is developed. An FPGA is programmed by simultaneously programming the antifuses in each programming set, the programming sets being programmed in the order they appear in the ordered list.

Method for simultaneous programming of multiple antifuses

A logic circuit is implemented on a macrocell of a field programmable device using select sets of a logic function which represents a transformation of the one or more input signals of the logic circuit to the output signal of the logic circuit. Select sets of a logic function are determined (i) by grouping input signals which correspond to equal co-factors of the logic function or (ii) by grouping input signals such that one input signal of a group never appears in a term of the logic function in a greedy phase-minimized RMF canonical form without all other input signals of the group. The logic circuit is implemented on a macrocell which includes a circuit element which selects one of two or more input signals according to one or more select signals, each of which is driven by a respective logic gate. Examples of such circuit elements include multiplexers and random access memory (RAM). The logic circuit is implemented by placing on input lines of a logic gate driving a select line the input signals or the complement of the input signals of a select set.

Select set-based technology mapping method and apparatus

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Fremont, CA, United States of America

Mukesh T Lulla