Intel Corporation

Apple Inc.

Mukesh Kataria

Joshua Resch

Jerrold Von Hauck

David W Grawrock

Mahesh S Natu

Michael Berger

Nitin V Sarangdhar

Robert J Royer, Jr

Eng Hun Ooi

Mazen G Gedeon

Michael N Derr

William A Stevens, Jr

Bruce Querbach

Purushottam Goel

Eli Elik Kupermann

Brian R Mcfarlane

Tieyu Zheng

Yasser Rasheed

Andrew H Gafken

Keshavan K Tiruvallur

Mark B Trobough

David Birnbaum

Michael Neve De Mevergnies

Chinna B Prudvi

Hermann Gartler

Vui Yong Liew

Alberto J Martinez

Kumar Narasimhan Dwarakanath

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Jeffrey Tripp

Jay Joseph Nejedlo

Lyle E Cool

Khee Wooi Lee

James J Grealish

Russell J Wunderlich

Abhijit Davare

Brian Meyer

Priyadarsan Patra

Neel Piyush Shah

Rahima K Mohammed

William Penner

Hung Huynh

Ridvan A Sahan

Yuen Tat Lee

John L Baudrexl

Vinupama Godavarthi

Arun R Ramadorai

Fred H Bolay

Wee Hoo Cheah

Kapila B Udawatta

Loren James McConnell

Kip C Killpack

Kyle Markley

Christian E Iovin

Selvakumar Raja Gopal

Robert Royer

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Tim Abels

Travis K Goff

Evan J Halprin

Jeffrey John Vick

Jiun Long Foo

Jr William A Stevens

Technologies disclosed herein provide an apparatus comprising a fuse controller coupled to an aggregator. The fuse controller includes a plurality of fuses for storing a unique identifier of a device and a first secured value of a first password associated with the unique identifier. The aggregator is to receive the unique identifier and the first secured value from the fuse controller, send the unique identifier to an unlock host, receive a second password from the unlock host, compute a second secured value of the second password using a security function, and unlock one or more privileged features on the device based on the first secured value corresponding to the second secured value. In a specific embodiment, the first secured value corresponds to the second secured value if the first password is equivalent to the second password.

Secure unlock systems for locked devices

An apparatus includes one or more functional circuits, a debug circuit configured to implement one or more debug features for the one or more functional circuits, and a validation circuit. The validation circuit is configured to receive a request to access debug features, and to send an identification value corresponding to the apparatus. The validation circuit is further configured to receive a certificate generated by a server computer system, the certificate including encoded debug permissions, and to decode the debug permissions using the identification value. Using the decoded debug permissions, the validation circuit is further configured to enable one or more of the debug features.

Authenticated debug for computing systems

A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.

In-system provisioning of firmware for a hardware platform

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

A processor has a limited set of guard bands that the processor uses, and when a certain amount of stress is accumulated as indicated by the cumulative stress counters (S), and the threshold for the current guard is about to be exceeded, the processor switches to the next wider guard band with this technique occurring until all the guard bands are used and end of life settings are reached. This data that can be stored in the FPFs, and in accordance with one exemplary embodiment, the guard band index itself is also stored in the FPFs and used to ensure the most accurate guard band is used by the processor/device.

Use of in-field programmable fuses in the PCH dye

A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.

Method and apparatus for write-only inter-processor reset synchronization

A platform including a security system is described. The security system comprises, in one embodiment, a multi-state system having a plurality of modes, available whenever the platform has a source of power. The modes comprise an unarmed mode, in which the security system is not protecting the platform, an armed mode, in which the platform is protected, the armed mode reached from the unarmed mode, after an arming command, and a suspecting mode, in which the platform is suspecting theft, the suspecting mode reached from the armed mode, when a risk behavior is detected.

Always-available embedded theft reaction subsystem

Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.

Tri-layered power scheme for architectures which contain a micro-controller

Embodiments include monitoring a computing system to determine whether firmware of the computing system is corrupted, hung up, or requires automatic update. The computing system may then request firmware update data over a network. Moreover, the computing system may include a controller with capability to determine whether the firmware is corrupted or hung and request and receive firmware update data over a network. In addition, the controller may have the capability operate when the firmware is corrupted or hung up, if the processor is held up, and if the operating system is halted, hung up, or soft-off. In addition, if the controller detects that the firmware is corrupted or hung up, the controller may halt the processor while updating the firmware.

Self-monitoring and updating of firmware over a network

Growing community of inventors

Santa Clara, CA, United States of America

Mukesh Kataria