Other

Nexabit Networks LLC

Axiowave Networks, Inc.

Neonet Lllc

Mukesh Chatter

Zbigniew Opalka

Peter Marconi

Rayadurgam Ravikanth

Kenneth J Schroder

Richard Conlin

Dimitry Haskin

Satish S Soman

Tim Wright

Jeffrey Parker

A method of and operating architectural enhancement for combining photonic and data packet-based networks to be unified or integrated as a single device and with a common software control plane, enabling increased utilization of such combined networks and in particular of optical path data flow capacity.

METHOD OF AND OPERATING ARCHITECTURAL ENHANCEMENT FOR COMBINING OPTICAL (PHOTONIC) AND DATA PACKET-BASED ELECTRICAL SWITCH FABRIC NETWORKS WITH A COMMON SOFTWARE CONTROL PLANE WHILE PROVIDING INCREASED UTILIZATION OF SUCH COMBINED NETWORKS

A novel chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through the appropriate buffers, the chip layout having, data ports substantially symmetrically placed with each data port connected to each arbitration unit and each transmit/receive buffer bank, and with each data port enabled to write into any DRAM bank, with the connections being effected such that each data port is substantially symmetric with respect to DRAM bank, arbitration unit and transmit/receive buffer banks and busses; and with timing clocks centrally placed on the chip to minimize clock skew by symmetric clock distribution.

Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like

Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like

A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called `AMPIC DRAM`, and consequentially a unique system architecture which eliminates current serious system bandwidth limitations, providing a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach, and with the chip also interconnecting significantly higher numbers of resources with substantially enhanced performance and at notably lower cost. Through use of a system configuration based on this novel architecture and working equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.

Multi-port internally cached DRAM system utilizing independent serial

A novel architecture for high speed dual symmetric full duplex operation of otherwise asymmetrical telephone subscribers--central office modems that provide relatively high data rate downloading from the telephone central office but relatively low data rate uploading from the subscriber stations, whereby, through direction swapping by such duplex operation, equal downloading and uploading can be achieved, or other increasing or grate swapping or variation of the uploading rate capability, as desired. ADSL modems in particular, being reconfigured to provide symmetrical rate downloading and uploading and/or configured direction assignment of rates.

Method of and system architecture for high speed dual symmetric full

A technique for configuring arrays of programmable logic cells, including those associated with FPGA devices, through a novel DRAM-based configuration control structure that enables not only 'on-the-fly' alterable chip and similar device reconfigurations, but, where desired, self-modifying reconfigurations for differing functionalities of the devices, eliminating current serious reconfigurability limitations and related problems, while providing significantly enhanced system performance at low cost. A large amount of memory is available internal to the FPGA and is accessed with a small number of pins such that the reconfiguration time is, for example, four orders of magnitude faster than the traditional approaches and at notably low cost.

High performance self modifying on-the-fly alterable logic FPGA,

A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called `AMPIC DRAM`, and consequentially a unique system architecture which eliminates current serious system bandwidth limitations, providing a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach, and with the chip also interconnecting significantly higher numbers of resources with substantially enhanced performance and at notably lower cost through the use of a system configuration based on this novel architecture and working equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.

Growing community of inventors

Hopkinton, MA, United States of America

Mukesh Chatter