Hewlett Packard Enterprise Development LP

Mujeeb Rehman

Melvin K Benedict

Chanh V Hua

Reza Mushtag Bacchus

Yuchen Xu

A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.

Differential serial memory interconnect

Example implementations relate to a system for enabling compression of a video output. For example, the system can include a circuit board including a plurality of slots, each slot to receive a module, a multiplexor coupled between the plurality of slots, and a management controller, among other components. The management controller can detect a respective type of module coupled to each of the plurality of slots and instruct the multiplexor to transmit signals between a first slot among the plurality of slots and a second slot among the plurality of slots in response to detection of a graphics coprocessor module coupled to the first slot and an accelerator module coupled to the second slot. Similarly, the management controller can compress a video output from the first slot using the second slot.

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Houston, TX, United States of America

Mujeeb Rehman