King Abdulaziz University

Muhyaddin Rawa

Hussain Bassi

Marif Daula Siddique

Noraisyah Binti Mohamed Shah

Saad Mekhilef

Yusuf Abdulaziz Al-Turki

Mengchu Zhou

Abdullah Abusorrah

Hesham Alhumade

Yam P Siwakoti

Aiiad Albeshri

N Sandeep

M Jagabar Sathik

Khaled Sedraoui

Xi Wang Guo

Kaustubh Bhatnagar

Ahmed Alabdulwahab

A multi-robotic U-shaped disassembly line, a method for disassembling components on the multi-robotic U-shaped disassembly line, and a non-transitory computer readable medium that cause one or more processors to perform the method for disassembling components on the multi-robotic U-shaped disassembly line are provided. The multi-robotic U-shaped disassembly line uses multiple robots, assigned to multiple workstations to perform disassembly tasks without precedence and conflict relationships, so that different types of end-of-life products can be disassembled. A mathematical model is established to maximize the disassembly profit and minimize the smoothness index for the multi-robotic U-shaped disassembly line. An Improved Multi-objective Discrete Brainstorming Optimization (IMDBO) algorithm is utilized to identify improvements for the multi-robotic U-shaped disassembly line.

System and methods for multi-robotic multi-product U-shaped disassembly line

A 15-level multilevel inverter circuit includes an outer circuit, an inner circuit, a polarity changing circuit and a computing device. The outer circuit and the inner circuit include a plurality of DC voltage supplies. Each DC voltage supply has a positive and a negative terminal. The outer circuit, the inner circuit and the polarity changing circuit include a plurality of unidirectional power switches. Each unidirectional power switch is a transistor with a diode connected in parallel to the transistor. The computing device is configured to provide control signals to the gates of the plurality of the unidirectional power switches of the outer circuit and the inner circuit to add or subtract the voltage of each of inner DC voltage supplies to form square waveforms approximating sinusoidal waveforms, and to the gates of the plurality of the unidirectional power switches of the polarity changing circuit to switch the polarity of the voltage.

Method for controlling output voltage at a multilevel inverter

A multi-level switched capacitor boost inverter includes a series connection of a two-switched capacitor circuit, a source module and at least one one-switched capacitor circuit. Level-shifted pulse width modulation is used to apply gate pulses to the switches. The multi-level switched capacitor boost inverter uses only three capacitors and a single DC voltage source to generate thirteen voltage levels at load terminals with a voltage gain of three. The capacitors of the two-switched capacitor circuit are self-balancing. Additional one-switched capacitor circuits can be added in series with the inverter. Each additional one-switched capacitor circuit increases the number of levels and increases the gain by one.

Method of operating a multi-level switched capacitor boost inverter

Microprocessor-controlled power system for a battery-powered multilevel inverter circuit

Switched capacitor multilevel inverter (SCMLI) configuration for high-frequency medium voltage applications is presented. A 5L-SCMLI basic configuration is further extended to 9L operation with a reduced number of active switches having self voltage boosting and balancing ability. Further, the proposed 9L-SCMLI is extended up to n level being considered as the basic configuration for the extension of horizontal extension (HE) and vertical extension (VE). A generalized switching table is provided for the proposed extensions. Design of the size of capacitor demonstrated for the proposed 9L-SCMLI.

Switched-capacitor multilevel inverter with self-voltage-balancing for high-frequency power distribution system

A multilevel inverter includes an inner DC source group circuit that generates a plurality of voltage levels, and an outer DC source group circuit that generates a substantially sinusoidal output voltage. The substantially sinusoidal output voltage is generated using, at least in part, the plurality of voltage levels generated by the inner DC source group circuit. An H-bridge circuit supplies the substantially sinusoidal output voltage at alternating polarities to a load.

Method for operating a multilevel inverter with a sinusoidal output voltage

An 11 level boost active neutral point clamped (BANPC) inverter using four capacitors and a single DC voltage source to generate eleven voltage levels at load terminals with a voltage gain of 2.5. A minimum of switching elements are used. Gate pulses for the switches are generated using nearest level control pulse width modulation (NLC-PWM). The capacitors of the 11 level boost active neutral point clamped inverter are self-balancing.

Method for generating output voltages with a boost inverter

11-level boost active neutral point clamped inverter topology with higher voltage gain

Multilevel inverter with reduced number of components

Flexible alternating current transmission system with multilevel inverter

Active neutral point clamped inverter with a plurality of boost levels

Load generation using a multi-level switched capacitor boost inverter

Switched capacitor based boost inverter topology with a higher number of levels and higher voltage gain

Multilevel inverter to generate an alternating current voltage from one or more direct current sources

Growing community of inventors

Jeddah, Saudi Arabia

Muhyaddin Rawa