Nxp B.v.

Nxp Usa, Inc.

Muhammed Bolatkale

Lucien Johannes Breems

Robert Rutten

Shagun Bajoria

Johannes Hubertus Antonius Brekelmans

Chenming Zhang

Manfred Zupke

Martin Kessel

Hendrik Van Der Ploeg

Bernard Burdiek

Jan Niehof

Mohammed Abo Alainein

Massimo Ciacci

Evert-Jan Pol

Maxim Kulesh

Johan Frederik Witte

Pierluigi Cenci

Soheil Bahrami

Albertus Willibrordus Oude Essink

Dongjin Son

A circuitis described comprising (i) a first digital-to-analog converter, (ii) a second digital-to-analog converter, (iii) a plurality of unit elements, and (iv) switching circuitry. The switching circuitryis adapted so that in a first switching state, a set of unit elementsof the plurality of unit elementsforms part of the first digital-to-analog converter, and in a second switching state, the set of unit elementsforms part of the second digital-to-analog converter. Furthermore, a corresponding method of operating a circuitis described.

Circuit with two digital-to-analog converters and method of operating such the circuit

There is described an analog-to-digital converter, ADC, device (), comprising:

Operating an analog-to-digital converter device

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.

Shuffler-free ADC error compensation

A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.

System and method of reducing delta-sigma modulator error using force-and-correction

There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.

Hybrid ADC circuit and method

Example aspects are directed to operating a SPAD receiver such as may be used in a light detection and ranging (Lidar) system. In one example, the SPAD receiver has SPAD circuitry for multiple photon detections using a single-channel TDC (time-to-digital converter), and such photon detection is quenched after detection so as to establish an effective pre-defined OFF period. In response, the SPAD circuitry is recharged for a subsequent ON period during which the SPAD circuitry is unquenched (or armed) for further photon detection and processing.

Photon-based detection using single-channel time-to-digital conversion

A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.

System and method of calibration of sigma-delta converter using tone injection

A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

System and method of calibration of sigma-delta converter using injected signal correlation

The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.

Techniques for high-speed excess loop delay compensation in sigma-delta analog-to-digital converters

A N-bit continuous-time sigma-delta modulator, SDM, () includes an input configured to receive an input analog signal (); a first summing junction () configured to subtract a feedback analog signal () from the input analog signal (); a loop filter () configured to filter an output signal from the first summing junction (): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal () to a digital output signal () where each 1-bit ADC comprises at least one pair of comparator latches (); and a feedback path () for routing the digital output signal to the first summing junction (). The feedback path () includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal () to an analog form. The ADC comprises or is operably coupled to, a calibration circuit () coupled to an input and an output of the at least one pair of comparator latches () and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches () in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

Sigma delta modulator, integrated circuit and method therefor

An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

Offset compensation in ADC circuitry

A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.

Metastability shaping technique for continuous-time sigma-delta analog-to-digital converters

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.

Signal processing and conversion

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

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Delft, Netherlands

Muhammed Bolatkale