Western Digital Technologies, Inc.

Qualcomm Incorporated

Muhammad Tauseef Rab

Deepak Panwar

Robert T Golla

Erich Plondke

Ajay Anant Ingle

Matthew B Smittle

Techniques are disclosed relating to using non-debug path circuitry to perform debug commands. In some embodiments, an apparatus includes a processor core that includes path circuitry configured to access data for instructions executed by the processor core and storage elements which the path circuitry is configured to access via one or more ports. In some embodiments, the apparatus includes debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the apparatus includes control circuitry in the processor core configured to, in response to an abstract command to access one or more of the storage elements: generate signaling to access the one or more storage elements using the path circuitry, access read data from the one or more storage elements based on the signaling, and transmit the accessed read data to the debug circuitry.

Debug command execution using existing datapath circuitry

Techniques are disclosed relating to speculative execution of store instructions. In various embodiments, an integrated circuit includes an execution pipeline having a load store circuit. The load store circuit is configured to receive a first store instruction executable to store a first value in a memory accessible to the integrated circuit. Prior to the first store instruction committing, the load store circuit stores the first value in a store buffer. In response to the first store instruction committing, the load store circuit stores, in the store buffer, an indication that the first store instruction has committed. In various embodiments, the integrated circuit reads the stored indication to determine whether the first store instruction has committed and, responsive to the read indication, provides the first value for storage in the memory.

Unified store buffer

A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.

Growing community of inventors

Austin, TX, United States of America

Muhammad Tauseef Rab