Cavium, Inc.

Cavium Networks, Inc.

Cisco Technology, Inc.

Marvell Asia Pte., Ltd.

Aol Inc.

Magiq Technologies, Inc.

Oavium Networks, Inc.

Cavium Networks, In.

Muhammad Raghib Hussain

Richard Eugene Kessler

Rajan Goyal

Faisal Masood

David Albert Carlson

Gregg Alan Bouchard

Vishal Murgai

Manojkumar Panicker

Trent Parker

Imran Badr

Robert A Sanzone

Brian Folsom

Philip H Dickinson

Amer Haider

Wilson Parkhurst Snyder, Ii

Harri Hakkarainen

Khaja E Ahmed

Michael D Varga

Michael S Bertone

Sudhir Tonse

Thomas Frederick Hummel

David C Sobotka

Daniel A Katz

Audrius Berzanskis

Aftab Zia

Christophe Joly

Leejay Wu

Mohan Rao

Brock D LaPorte

M Sultan Khan

Keun Lee

Imrar Badr

Yen Lee

A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented on a chip, to a target entity, is disclosed. Additionally, the system embodying a method for network switching of a data packet outgoing from an internal facing interface of a network interface controller portion of the network interface resource to a network is disclosed.

Network switching with co-resident data-plane and network interface controllers

A processor device comprises a plurality of virtual systems on chip, configured to utilize resources of a plurality of resources in accordance with a resource alignment between the plurality of virtual systems on chip and the plurality of resources. The processor device may further comprises a resource aligning unit configured to modify the resource alignment, dynamically, responsive to at least one event. Modifying the resource alignment, dynamically, may prevent a loss in throughput otherwise effectuated by the at least one event.

Method and apparatus for dynamic virtual system on chip

A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a method that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the method for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.

Method and apparatus for a virtual system on chip

A new approach is proposed that contemplates systems and methods to support hardware-based Quality of Service (QoS) operations, which offloads metering functionalities under OpenFlow protocol to a programmable hardware unit/block/component. The hardware unit supports several hardware implemented ports and each port supports multiple configurable queues for the packet flows through a network switch/chip/system. Specifically, the hardware unit includes a plurality of descriptor queues (DQs) configured to accept requests to send a plurality of packets from one or more CPU cores, and a plurality of condition and schedule modules configured to meter, schedule, and condition the packets through a hierarchy of scheduling queues under one or more metering constraints. The hardware unit is programmable to configure the byte-based and/or packet-based rate-limit for each of the packet flows with a calculated adjustment on allowed variations without requiring complex QoS algorithms to maintain the rate-limits of the flows.

Systems and methods for hardware accelerated metering for openflow protocol

A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.

Method and apparatus for virtualization

A new approach is proposed that contemplates systems and methods to support hot plugging and/or unplugging one or more of remote storage devices virtualized as extensible/flexible storages and NVMe namespace(s) via an NVMe controller during operation. First, the NVMe controller virtualizes and presents a set of remote storage devices to one or more VMs running on a host attached to the NVMe controller as logical volumes in the NVMe namespace(s) so that each of the VMs running on the host can access these remote storage devices to perform read/write operations as if they were local storage devices. When the one or more remote storage devices are added to or removed from the set of remote storage devices based on storage space needs of the VMs, the NVMe controller updates the logical volumes in the NVMe namespace(s) accordingly and enables these remote storage devices to be hot plugged or unplugged from the plurality of remote storage devices at runtime without requiring shutting down and restarting any of the VMs, the host, and/or the NVMe controller. The VMs may then perform read/write operations on the NVMe namespace(s) updated to reflect the changes in the configuration of the set of remote storage devices dynamically without any interruption.

Systems and methods for supporting hot plugging of remote storage devices accessed over a network via NVME controller

In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.

Graph caching

A semiconductor includes a set of protected hardware resources, where at least one protected hardware resource stores a secure key. The semiconductor also includes a computation kernel and a memory to store a resource enablement module executed by the computation kernel. The resource enablement module selectively enables a protected hardware resource in response to a delivered key corresponding to the secure key.

Apparatus and method for software enabled access to protected hardware resources

An apparatus includes a Media Access Control (MAC) scheduler to generate a priority value calculation request with a specified formula and a list of metrics. A hardware based priority value calculation coprocessor services the priority value calculation request in accordance with the specified formula and the list of metrics.

Apparatus and method for media access control scheduling with a priority calculation hardware coprocessor

An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.

Content search pattern matching using deterministic finite automata (DFA) graphs

Authenticated hardware and authenticated software are cryptographically associated using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. In one embodiment, critical security information associated with the equipment is loaded from a memory at startup time. The critical security information is stored in the memory, in encrypted form, using a unique secret value. The secret value is used to retrieve a chip encryption key and one or more image authentication keys that can be used to associate program code with an original equipment manufacturer. These keys are used to authenticate the program code.

Secure software and hardware association technique

A new approach is proposed to support a virtual network switch, which is a software implementation of a network switch utilizing hardware to accelerate implementation of timers of the virtual network switch under OpenFlow protocol. The approach utilizes a plurality of hardware-implemented timer blocks/rings, wherein each of the rings covers a specified time period and has a plurality of timer buckets each corresponding to an interval of expiration time of timers. When a new flow table entry is programmed at an OpenFlow agent of the virtual network switch, its associated timer entries are created and inserted into the corresponding timer bucket based on the expiration time of the timers. During operation, hardware of the virtual network switch traverses the timer rings for the timer bucket which time has expired, identifies timer entries in the expired timer bucket, interrupts CPU or provides a notification to the agent with necessary contextual information.

Systems and methods for hardware accelerated timer implementation for openflow protocol

A new approach is proposed that contemplates systems and methods to support elastic (extensible/flexible) storage access in real time by mapping a plurality of remote storage devices that are accessible over a network fabric as logical namespace(s) via a logical storage controller using a multitude of access mechanisms and storage network protocols. The logical storage controller exports and presents the remote storage devices to one or more VMs running on a host of the logical storage controller as the logical namespace(s), wherein these remote storage devices appear virtually as one or more logical volumes of a collection of logical blocks in the logical namespace(s) to the VMs. As a result, each of the VMs running on the host can access these remote storage devices to perform read/write operations as if they were local storage devices via the logical namespace(s).

Systems and methods for enabling access to extensible remote storage over a network as local storage via a logical storage controller

Growing community of inventors

Saratoga, CA, United States of America

Muhammad Raghib Hussain