Intel Corporation

Other

Muhammad M Khellah

Vivek K De

Yibin Ye

Dinesh Somasekhar

Stephen H Tang

James W Tschanz

Ali Keshavarzi

Fabrice Paillet

Charles Augustine

Jaydeep P Kulkarni

Shih-Lien L Lu

Somnath Paul

Carlos Alfonso Tokunaga

Anupama Ambardar Thaploo

Tanay Karnik

Christopher B Wilkerson

Fatih Hamzaoglu

Ming Lei Zhang

Yih Wang

Iqbal Rajwani

Antonio Gonzalez

Xavier Vera

Javier Carretero Casado

Jaume Abella

Eric C Samson

Gerhard Schrom

Arijit Raychowdhury

Brian S Doyle

Subramaniam M Maiyuran

Suman Datta

Ram K Krishnamurthy

Kevin X Zhang

Wei Wu

Alaa R Alameldeen

Ashish V Choubal

Altug Koker

Patrick R Morrow

Rafael Rios

Stefan Rusu

Nasser A Kurd

Lakshminarayanan Striramassarma

Bhushan M Borole

Sriram R Vangal

Zeshan A Chishti

Tobias Bocklet

Andrew M Lines

Patrick Koeberl

Pascal Meinerzhagen

Suyoung Bang

Bibiche M Geuskens

Minki Cho

Nam Sung Kim

Turbo Majumder

Stephen Kim

Mohsen Alavi

Pedro Chaparro Monferrer

George Shchupak

Pascal A Meinerzhagen

Maged Ghoneima

Sadique Ul Ameen Sheik

Wootaek Lim

Arvind Raman

Gunjan H Pandya

Moty Mehalel

Yong Shim

Amit R Trivedi

DiaaEldin S Khalil

Eric A Karl

Rinkle Jain

Chen Koren

Bo Zheng

Feroze Merchant

Karthik Subramanian

Peter Caputa

Yehea I Ismail

Yi-Chun Shih

Abdullah Afzal

Kyung-Hoae Koo

Yiben Ye

Kaushik Mazumdar

Andres Malavasi Mora

Praveen Mosalikanti

Jawad Nasrullah

Oren Arad

Pratik A Patel

Mircea R Stan

Cyrille Dray

Chris Wilkerson

Binuraj K Ravindran

David Pearce

Nathaniel August

Kelvin Kwan

Lei Jiang

Eric Kwesi Donkoh

Pulkit Jain

Ali R Farhang

Miguel Bautista Gabriel

Surya Sasi Kiran Tallapragada

Daivik H Bhatt

Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying Mmetal layer and an underlying BMmetal layers to reduce capacitance.

SRAM with P-type access transistors and complementary field-effect transistor technology

A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

Circuits and methods for supply voltage detection and timing monitoring

Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

Unified retention and wake-up clamp apparatus and method

Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

Energy efficient memory array with optimized burst read and write data access

A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

Distributed and scalable all-digital low dropout integrated voltage regulator

A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.

Concurrent compute and ECC for in-memory matrix vector operations

Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

Current steering level-shifter

An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.

Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation

An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

All-digital closed loop voltage generator

An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

All-digital voltage monitor (ADVM) with single-cycle latency

Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

Techniques for multi-read and multi-write of memory circuit

An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.

Reliable digital low dropout voltage regulator

An apparatus, vision processing unit, and method are provided for clustering motion events in a content addressable memory. A motion event is received including coordinates in an image frame that have experienced a change and a timestamp of the change. A determination is made as to whether determine whether there is a valid entry in the memory having coordinates within a predefined range of coordinates included in the motion event. In response to a determination that there is the valid entry having the coordinates within the predefined range of coordinates included in the motion event, write to the valid entry the coordinates and the timestamp in the motion event.

Apparatus, video processing unit and method for clustering events in a content addressable memory

A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.

Post synaptic potential-based learning rule

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Lake Oswego, OR, United States of America

Muhammad M Khellah