Gte Automatic Electric Incorporated

Gte Communication Systems Corporation

Muhammad I Khera

Thomas J Perry

A dynamic RAM refresh circuit provides the interface for timely refresh of up to 64K of RAM memory while simultaneously providing for minimal disruption of a CPU's access of that RAM memory. Circuitry is also provided to permit interlock control for timeshared access of the RAM memory on a shared basis with the refresh circuit.

Dynamic RAM refresh circuit

This circuit provides a scheme for protecting a common dynamic memory of a distributed processing system. This circuit protects against premature completion of a memory access cycle by a CPU for any of a number of fault conditions. As a result, common memory integrity is maintained despite a high number of memory accesses by a number of CPUs. This circuit operates in a simplex configuration or a duplicated redundant configuration.

Anti-mutilation circuit for protecting dynamic memory

A formatted data message for conveying control information from the peripheral processor of one telecommunications switching system to the peripheral processor of at least one other telecommunications switching system is provided. The data message format comprises a first control work including a plurality of control bits, a data bit and a parity bit for the first control word and a plurality of data words, each data word including a parity bit. The data words contain control information to be conveyed to the receiving peripheral processor. A parity word is included which provides parity for an associated plurality of the preceding data and control words.

Data format arrangement for communication between the peripheral

A receive data reformatter for a telecommunications switching system is shown for disassembling a data message to a plurality of 8-bit data bytes. The receive data reformatter is comprised of a parallel to serial converter which receives the data message one byte at a time which it subsequently outputs serially. A horizontal parity check circuit receives the serial data and is arranged to output an error signal when an error in parity is detected. A serial to parallel converter, connected to the serial output of the parallel to serial converter, receives the serial data and assembles the serial data into parallel form. A write buffer connected to the serial to parallel converter receives the assembled parallel data when eight data bits have been accumulated in the serial to parallel converter. The thus formed data byte is output to a peripheral processor of the telecommunications switching system.

Remote data link receive data reformatter

A transmit data formatter is provided for assembling a plurality of 8-bit data bytes into a data message containing a plurality of message bytes. The transmit data formatter includes a receive buffer which receives a data byte from a peripheral processor. A parallel to serial converter receives the data byte from the receive buffer and outputs the data byte serially. A serial to parallel converter receives the serial data byte and assembles the data byte into a partial message byte when seven data bits have been received. A horizontal parity generator connected to the parallel to serial converter develops a horizontal parity bit which is appended to the seven data bits forming a message byte.

Remote data link transmit data formatter

An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link processor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.

Remote data link address sequencer and a memory arrangement for

A remote data link controller is disclosed for formatting, transmitting and receiving control data over high speed digital data links between the peripheral processors of a plurality of telecommunications switching systems. The remote data link controller includes a microprocessor controlled data link processing circuit which is time shared among all of the digital data links. The remote data link controller processes one transmit and one receive message byte during a reformatting cycle for each digital data link. It stores any intermediate results in a temporary memory than proceeds to service the next digital data link. The remote data link controller fetches intermediate results from the temporary memory, processes the data and stores the next intermediate results in the temporary memory until it has completely serviced all of the digital data links.

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Glendale, AZ, United States of America

Muhammad I Khera