Movellus Circuits Inc.

University of Michigan

Muhammad Faisal

Jeffrey Alan Fredenburg

David Michael Moore

Ramin Shirani

David D Wentzloff

Yu Huang

An integrated circuit (IC) includes multiple interconnected driver cells enabled/disabled based on a first set of control signals. The multiple circuit cells are arranged to define a first aggregate enabled/disabled configuration exhibiting a first aggregated delay. The first aggregated delay is based on the individual enabled/disabled states of the circuit cells. Timing circuitry evaluates the first aggregate delay with respect to a circuit design constraint, and selectively generates a second set of control signals to configure the multiple circuit cells to define a second aggregate enabled/disabled configuration having a second aggregate delay different than the first aggregate delay.

Timing analysis for parallel multi-state driver circuits

A computer-implemented method for manufacturing an integrated circuit chip is disclosed. The method includes selecting cell-based circuit representations to define an initial circuit design. The initial circuit design is partitioned into multiple sub-design blocks to define a partitioned design. Circuit representations of local clock sources are inserted into the partitioned design. Each local clock source is for clocking a respective sub-design block and based on a global clock source. A timing analysis is performed to estimate skew between each local clock source and the global clock source. The partitioned design is automatically modified based on the estimated skew.

Integrated circuit design system with automatic timing margin reduction

An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.

A computer-implemented method for manufacturing an integrated circuit chip includes generating a timing model for a first circuit description of an analog parallel multi-state driver circuit. The first circuit description of the analog parallel multi-state driver circuit having programmable driver states. The timing model is dependent on the driver states. The first circuit description of the analog parallel multi-state driver circuit and the generated timing model are provided for insertion into a second circuit description representing a digital system.

Timing analysis for electronic design automation of parallel multi-state driver circuits

A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.

Locked loop circuit with configurable second error input

A reconfigurable frequency and delay generator is disclosed, and a representative embodiment may include a phase sampler and plurality of configurable oscillator stages, each configurable oscillator stage of the plurality of configurable oscillator stages comprising: a plurality of core inverters coupled in series, a last core inverter of the plurality of core inverters generating an output signal having a configurable output frequency; and a plurality of delay control circuits, each delay control circuit of the plurality of delay control circuits coupled to an output of a corresponding core inverter of the plurality of core inverters.

Digital, reconfigurable frequency and delay generator with phase measurement

A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.

Concurrently optimized system-on-chip implementation with automatic synthesis and integration

A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.

Reconfigurable phase-locked loop

A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and delay generator is configured as the delay line circuit.

Reconfigurable phase-locked loop with optional LC oscillator capability

A reconfigurable digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator to generate an input signal having a reference frequency. A representative embodiment of the reconfigurable digital phase-locked loop integrated circuit may include a first digital phase-locked loop circuit configured to generate a first signal having a first frequency which is an integer multiple of the reference frequency; and a second digital phase-locked loop circuit coupled to the first digital phase-locked loop, the second digital phase-locked loop configured to generate a second, output signal having a second output frequency in response to a plurality of configuration parameters, the second frequency having a configurable fractional offset from the integer multiple of the reference frequency, and to match a phase of the second output signal with a first signal phase.

Fractional and reconfigurable digital phase-locked loop

A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region.

Dual-loop programmable and dividerless clock generator for ultra low power applications

An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (f) at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to multiple tunable delay elements; receiving at the multiple tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output (f) to the TDC at least partially based on the first signal input; and generating a phase error output (&#x3a6;) based on the reference signal (f) and the PLL output (f), wherein the phase error output (&#x3a6;) is provided as feedback to the controller to control the PLL output (f).

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Ann Arbor, MI, United States of America

Muhammad Faisal