Industrial Technology Research Institute

Midastek Microelectronic Inc.

Other

Computer & Communication Research Laboratories

Muh-Rong Yang

Gin-Kou Ma

Chiung-Shien Wu

Yun-Yen Chen

Well-Chen Chua

Wen-Chung Liu

Chi-Chien Lin

Po-Tsun Chen

Ho-Chi Hwang

Wen-Chang Yu

Mao-Chuan Chien

A current sensing module and a power conversion apparatus and an electronic apparatus using the same are provided. The current sensing module is suitable for detecting a first load current flowing through a first load. The current sensing module includes a sampling stage circuit and an output stage circuit. The sampling stage circuit couples across the first load and selectively exchanges coupling nodes between the sampling stage circuit and the first load by a multiplex switching means, so as to sample the first load current flowing along a first direction or a second direction, and thus generate a sampling signal. The output stage circuit is coupled to the sampling stage circuit and switches coupling nodes between the output stage circuit and the output terminal of the sampling stage circuit, so as to generate a current indication signal indicating the magnitude of the first load current according to the sampling signal.

Current sensing module and power conversion apparatus and electronic apparatus using the same

A smart power adaptor and a method of controlling power supply thereof are provided. The smart power adaptor includes a power conversion circuit and a control unit. The power conversion circuit is configured to convert an alternating current (AC) power into a direct current (DC) power for providing to a load device. The control unit is coupled to the power conversion circuit. The control unit is configured to apply a corresponding power-supply control mean according to a power state through communication of a charging communication protocol of a battery module of the load device to control an operation of the power conversion circuit, so that the power conversion circuit uses different power conversion behaviors to generate the DC power in response to changing of the power status.

Smart power adaptor and method for controlling power supplay thereof

A reference power generating circuit and an electronic circuit using the same are provided. The reference power generating circuit includes a first bandgap reference circuit and a second bandgap reference circuit. The first bandgap reference circuit is biased by a power voltage to generate a first reference voltage, where the first reference voltage has a first offset. The second bandgap reference circuit is connected to the first bandgap reference circuit in series and receives the first reference voltage generated by the first bandgap reference circuit. The second bandgap reference circuit is biased by the first reference voltage to generate a baseline reference voltage. The baseline reference voltage has a second offset, and the second offset is smaller than the first offset.

Reference power generating circuit and electronic circuit using the same

A transmission method executed in a multiple input multiple output wireless communication system may include the following steps: receiving a transmitting bit sequence; providing an X level pulse amplitude modulation (X-PAM) signal set, wherein distances between any two adjacent signal points in the X-PAM are the same; generating M signal sets according to the X-PAM signal set, wherein the isignal set is formed by multiplying the X-PAM signal set with a parameter (1/X), wherein i is an integer from 1 to M, and generating a X-PAM signal set joint coding/decoding table according a superposition result of the M signal sets; generating M transmitting bit sub-sequences according to the transmitting bit sequence; generating M transmitting signals according to the M transmitting bit sub-sequences and the X-PAM signal set joint coding/decoding table; transmitting the M transmitting signals to a wireless transmission channel via M transmitting antennae.

Transmission method and multiple input multiple output wireless communication system using the same

A method for receiving data is provided. Multiple packages are received according to a sliding window W(N). If a starting package of the packages is received successfully, the W(N) is slid to a W(N+1). If a non-starting package of the packages is received successfully, the corresponding counter is activated for counting. If the starting package of the packages is not successfully received and part of multiple counters counts to an up-limited value, the W(N) slides to the W(N+1). Other packages are continuously received according to the W(N+1), and whether the block sequence numbers (BSNs) of the counters located in the overlap area between the W(N) and the W(N+1) are determined. When at least one BSN to which at least one counter corresponds is not located in the overlap area, the at least one counter corresponding to the at least one BSN not located in the overlap area is reset.

Method for receiving data and communication device

A code tracking system and method especially for use in direct sequence code division multiple access (DS-CDMA) communication systems employs multiple timing references within a chip by tracking the multiple timing references relative to the exact midpoint of the chip, then adjusting the timing references to the exact midpoint of the chip, and outputting an error tracking signal in accordance with the minimum error associated with the multiple timing references. The system performs effective code tracking with low lock-loss rate even when the noise of a receiving path interferes with detection of some of the timing references. The system uses multiple delay-locked loops for the different timing references.

Delay lock code tracking loop employing multiple timing references

The present invention provides an apparatus and method for code group identification and frame synchronization for cell searching used in wide-band DS-CDMA cellular systems. This method characterizes each secondary synchronization code sequence (SSCS) with a corresponding theoretical frequency sequence, which represents the occurrence times of CS to CS in a corresponding SSCS. Thus, 64 secondary synchronization code sequences corresponding to 64 code groups defined in DS-CDMA systems also corresponds to 64 theoretical frequency sequences. By characterizing the SSCS transmitted by a base station, a real frequency sequence can be generated. Comparing the real frequency sequence with the 64 theoretical frequency sequences, one can determine one or two candidate code groups, which may be employed by the base station. Finally, one can compare the SSCS transmitted by the base station with all the possible SSCSs corresponding to the candidate code groups to determine a specific code group and a frame boundary for the base station.

Method and apparatus for code group identification and frame synchronization in DS/CDMA systems

A scalable server architecture for use in implementing scaled media servers capable of simultaneous real-time data stream retrieval for large numbers of subscribers. A scalable server includes a plurality of stream pumping engines each accessing a particular storage device of a storage subsystem, and a server processor which receives retrieval requests from subscribers and directs the stream pumping engines to retrieve the requested data streams. Each of the stream pumping engines may include a storage controller coupled to its corresponding storage device for directing retrieval of the requested stream therefrom, a network controller for supplying the retrieved stream to a client network, and a processor for directing the operation of the storage and network controllers. Each of the stream pumping engines may also include a shared memory accessible by the corresponding stream pumping engine processor and the server processor. The shared memory facilitates communication with other stream pumping engines via the server processor and server system bus. A scaled media server may be implemented by cross-connecting several scalable servers with a plurality of stream multiplexers. Each of the stream multiplexers can include a separate packet input unit for processing the packets of each media stream such that two distinct levels of transmission priority are provided and quality of server restrictions are satisfied for all streams.

Scalable architecture for media-on demand servers

A system and method are provided for routing received cells through a switch fabric. A plurality of output channels are organized into a plurality of channel groups, wherein each of the channels groups is associated with one or more unique output ports of a Benes network. A plurality of cells destined to one or more of the plurality of channel groups is received at plural input queues. A different output port of the Benes network is selected for one or more of the input queues that contains a cell. Then, one cell is switched from each of one or more input queues through the Benes network to the respective selected output port.

Multiple channel ATM switch

Scalable architecture for media-on-demand servers

A system and method are provided for assigning routing tag bits for routing signals through a Benes network comprising an input stage and an output stage. The input and output stages each comprise a column of 2.times.2 .beta. elements which route an inputted signal to an upper output if the control sequence bit is 0 and to a lower output if the control sequence bit is 1. Each signal inputted to the Benes network is associated with control sequence. For a particular Benes, in a particular control stage of the Benes network, a 0 is assigned to a control sequence bit associated with a signal q.sub.0 received at an upper input of a topmost input stage .beta. element. A 1 is assigned to a control sequence bit associated with a signal q.sub.k received at the same output stage p element as the signal q.sub.0. A 1 is assigned to a control sequence bit associated with a signal q.sub.1 received at a lower input of the topmost input stage .beta. element. A 0 to is assigned to a control sequence bit associated with a signal q.sub.k ' received at the same output stage .beta. element as the signal q.sub.1. For at least one signal q.sub.p for which no control sequence bit is yet assigned, either a 0 or a 1 is assigned to the control sequence bit associated with the signal q.sub.p. The complement of the chosen control sequence bit is assigned to a control sequence bit associated with a signal q.sub.k ' received at the same output stage .beta. element as the signal q.sub.p.

Enhanced partially self-routing algorithm for controller Benes networks

A method and apparatus for storage and retrieval of multiple data streams in a multimedia distribution system. A given data stream is separated into a plurality of portions, and the portions are stored in a multi-disk storage system with Y disks each having X zones such that the ith portion of the given stream is stored in zone (i mod X) of disk (i mod Y). The number X of zones per disk and the number Y of disks are selected as relatively prime numbers. The stored data are retrieved using Y independent retrieval schedulers which are circulated among the Y disks over a number of scheduling intervals. Each retrieval scheduler processes multiple requests separated into X groups, with the requests of each group accessing the same disk zone during a given scheduling interval. The retrieval schedulers are also configured such that the retrieval requests of a given retrieval scheduler access the same disk during a given scheduling interval. The data stream placement technique in conjunction with the retrieval schedulers provide sequential-like parallel retrieval suitable for supporting real-time multimedia data distribution for large numbers of clients.

Media server for storage and retrieval of voluminous multimedia data

An inventive switch for transporting information cells without cell contention is described. The switch includes at least one parallel distribution network. Each distribution network includes an N.times.N first routing network for receiving cells at a plurality of input ports, where N equals the number the input ports. Illustratively, the routing network is self-routing and non-blocking, such as a Banyan Network. Connected to the N.times.N network are .rho..sup.k groups of shared buffers for storing the cells routed through the network for a period of time not greater than one cell cycle, where k is incremented from 1 to �log.sub.2 N/log.sub.2 .rho.!.sup.-1 and .rho. equals a predetermined speed-up factor. In one aspect of this embodiment, the number of shared buffers is simply equal to N/.rho.. To prevent cell contention and cell loss, all of the contentious cells (cells destined for the same output during the same cycle) are stored in the same shared buffer. Connected to the shared buffers are .rho..sup.k groups of (N/.rho..sup.k).times.(N/.rho..sup.k) routing networks each having a plurality of output ports for outputting the cells, stored in the shared buffers, based on the destination addresses of each cell. Due in part to the utilization of .rho..sup.k groups of shared buffers, a large reduction in both hardware costs and chip real estate is realized. Specifically, a decrease in the number of switching stages is achieved.

Growing community of inventors

Taipei, Taiwan

Muh-Rong Yang