Apple Inc.

Muawya M Al-Otoom

Ian D Kountanis

Conrado Blasco

Deepankar Duggal

Niket K Choudhary

Pruthivi Vuyyuru

Kulin N Kothari

Ronald P Hall

Richard F Russo

Amit Kumar

Wei-Han Lien

Michael Lance Karm

Nikhil Gupta

Douglas C Holman

Haoyan Jia

Ethan R Schuchman

Ilhyun Kim

Disclosed techniques relate to branch prediction and trace caching. A processor may include both an instruction cache and a trace cache configured to store instructions. A branch predictor may include one or more prediction tables (e.g., tagged geometric length (TAGE) tables) configured to predict directions of conditional control transfer instructions. Rather than including a separate branch predictor for branches in the trace cache, the processor may share the prediction table(s) for instruction cache and trace cache predictions. In particular, the processor may include an additional trace prediction lane configured to access the prediction table to predict a direction of a final control transfer instruction in a trace cached by the trace cache circuitry. This may advantageously provide accurate predictions with limited impacts to circuit area and power consumption, e.g., relative to a separate predictor for the trace cache.

Sharing branch predictor resource for instruction cache and trace cache predictions

Disclosed techniques relate to next fetch predictor circuitry configured to operate in conjunction with a trace cache. The trace cache circuitry may identify and store traces of instructions based on predicted directions of one or more control transfer instructions. Trace next fetch predictor circuitry may predict a next fetch address based on a current fetch address for a current cycle, which may include predicting a next fetch address following execution of a first trace stored in the trace cache circuitry. The first trace may include multiple fetch groups and multiple control transfer instructions. Arbitration circuitry may select from among multiple predictors and the trace next fetch predictor may have priority in response to a trace cache hit. Disclosed techniques may advantageously improve overall fetch bandwidth in the context of trace cache hits.

Next fetch predictor for trace cache

An apparatus includes a processor core that includes an instruction decode circuit and a control circuit. The instruction decode circuit is configured to decode instructions, including a plurality of store instructions used to store information in a memory hierarchy. The control circuit is configured, after a particular store instruction is decoded, to preserve store information related to the particular store instruction, including a first program counter value for the particular store instruction. In response to decoding a subsequent load instruction with a corresponding second program counter value, the control circuit is configured to determine, using the first and second program counter values, whether a dependency has been established between the subsequent load instruction and the particular store instruction. In response to a determination that the dependency has been established, the control circuit is configured to use the preserved store information to perform the subsequent load instruction.

Program counter zero-cycle loads

Disclosed techniques relate to trace caches. Trace cache circuitry may identify traces that satisfy one or more criteria. Generally, internal branches of a trace should satisfy a threshold bias level in a particular direction. To achieve this goal, the processor may initially assume that branches meet the threshold, track their usefulness in the trace context over time, and prevent inclusion of branches that fall below a usefulness threshold (which indicates that those branches are not sufficiently biased). Branches that do not meet the threshold may be added to a Bloom filter, for example. Usefulness may be tracked during trace training, when valid in a trace cache, or both.

Trace cache with filter for internal control transfer inclusion

A multi-degree branch predictor is disclosed. A processing circuit includes an instruction fetch circuit configured to fetch branch instructions, and a branch prediction circuit having a plurality of prediction subcircuits. The prediction subcircuits are configured to store different amounts of branch history data with respect to other ones, and to receive an indication of a given branch instruction in a particular clock cycle. The prediction subcircuits implement a common branch prediction scheme to output, in different clock cycles, corresponding predictions for the given branch instruction using the different amounts of branch history data and cause, instruction fetches to be performed by the instruction fetch circuit. The prediction subcircuits are also configured to override, in subsequent clock cycles, instruction fetches caused by prediction subcircuits with comparatively less branch history data based on contrary predictions performed in subsequent clock cycles by prediction subcircuits with more branch history data.

Multi-degree branch predictor

Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event, determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

Multi-table signature prefetch

Systems, apparatuses, and methods for implementing zero cycle load bypass operations are described. A system includes a processor with at least a decode unit, control logic, mapper, and free list. When a load operation is detected, the control logic determines if the load operation qualifies to be converted to a zero cycle load bypass operation. Conditions for qualifying include the load operation being in the same decode group as an older store operation to the same address. Qualifying load operations are converted to zero cycle load bypass operations. A lookup of the free list is prevented for a zero cycle load bypass operation and a destination operand of the load is renamed with a same physical register identifier used for a source operand of the store. Also, the data of the store is bypassed to the load.

Zero cycle load bypass in a decode group

In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.

Indirect branch predictor based on register operands

Systems, apparatuses, and methods for implementing a physical register last reference scheme are described. A system includes a processor with a mapper, history file, and freelist. When an entry in the mapper is updated with a new architectural register-to-physical register mapping, the processor creates a new history file entry for the given instruction that caused the update. The processor also searches the mapper to determine if the old physical register that was previously stored in the mapper entry is referenced by any other mapper entries. If there are no other mapper entries that reference this old physical register, then a last reference indicator is stored in the new history file entry. When the given instruction retires, the processor checks the last reference indicator in the history file entry to determine whether the old physical register can be returned to the freelist of available physical registers.

History file for previous register mapping storage and last reference indication

A system and method for efficiently reducing the latency and power of memory access operations. A processor includes a stack pointer (SP) load-store dependence (LSD) predictor which predicts whether a memory dependence exists on a store instruction. The processor also includes a register file (RF) LSD predictor which predicts whether a memory dependence exists on a store instruction or a load instruction by a subsequent load instruction in program order. Each of the SP-LSD predictor and the RF-LSD predictor predicts and performs register renaming in a pipeline stage earlier than a renaming pipeline stage. The RF-LSD predictor also determines whether any intervening instructions between a producer memory instruction and a consumer memory instruction modify a predicted dependence.

System and method for predicting memory dependence when a source register of a push instruction matches the destination register of a pop instruction

In some embodiments, a branch prediction unit includes a plurality of branch prediction circuits and selection logic. At least two of the branch prediction circuits are configured, based on an address of a branch instruction and different sets of history information, to provide a corresponding branch prediction for the branch instruction. At least one storage element of the at least two branch prediction circuits is set associative. The selection logic is configured to select a particular branch prediction output by one of the branch prediction circuits as a current branch prediction output of the branch prediction unit. In some instances, the branch prediction unit may be less likely to replace branch prediction information, as compared to a different branch prediction unit that does not include a set associative storage element. In some embodiments, this arrangement may lead to increased performance of the branch prediction unit.

Branch prediction system

An example apparatus includes a plurality of execution units, a physical register file that includes a plurality of physical registers, an instruction buffer, and a scheduling circuit. The instruction buffer may receive a group of instructions to be performed by the plurality of execution units. The scheduling circuit may allocate a physical register of the plurality of physical registers in the physical register file to store an operand of a particular instruction of the group of instructions. The scheduling circuit may also, in response to determining that a result of the particular instruction is used as an operand for a different instruction of the group of instructions, assign a tag to the particular instruction and to the different instruction to indicate that the result of the particular instruction will be sent to the different instruction without using the physical register file.

Register allocation using physical register file bypass

Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

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Pleasanton, CA, United States of America

Muawya M Al-Otoom