International Business Machines Corporation

Mu-Yue Hsiao

Chin-Long Chen

William Wu Shen

Douglas Craig Bossen

Patrick James Meaney

Walter Heinrich Lipponer

Ricky A Rand

James Michael Mulligan

Douglas S Goodman

Paul Vincent McCann

Fuad Elias Doany

Frederick Hayes Dill

Charles F Pells

Klaus Ruediger Baat

Fredrick Hayes Dill

Douglas D Bossen

Surasak K O'Trakoun

Ralf J Terbruggen

Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.

Generating special uncorrectable error codes for failure isolation

An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.

Single symbol correction double symbol detection code employing a modular H-matrix

Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.

Method system and program products for error correction code conversion

Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.

Detecting address faults in an ECC-protected memory

A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

Method for writing single width bar codes on semiconductors wafers

An apparatus and method is discussed using a parity check matrix in order to acheive correction and detection of errors particularly pertaining to detection data fetched from a wrong address. The code structure enhances utilization of chip reliability by encoding and decoding digital signals through the utilization of a parity check matrix and parity bits generated from system address bits of a computer system with k symbols and b bits per symbol.

Memory implemented error detection and correction code capable of

A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of '1' or a low value of '0'. At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.

Memory implemented error detection and correction code using memory

Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a single bit error in another symbol for use in computer memory systems. The code structure enhances utilization of chip real estate and specifically provides for the utilization of a (76,64) code which employs 19 chips per computer memory word as opposed to 20 chips per word.

Error detection and correction for four-bit-per-chip memory system

A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of '1' or a low value of '0'. At least one address parity bit is then generated from each group and used in checking the integrity of data received.

Memory implemented error detection and correction code with address

A barcode scanner, which is particularly suitable for reading barcode information from surfaces having various reflective properties, includes a light intensity control for the light source of the barcode scanner. The light intensity control preferably comprises a means for ramping voltage and a summing circuit which allows the current flowing through the light source to be controlled. In addition, the light intensity control utilizes a clocking means which controls the rate of voltage ramping.

Barcode scanner with adjustable light source intensity

Presence/absence bar code

A method and apparatus reliably and robustly decode single width bar codes that may be placed on a variety of materials. The decoding is independent of whether or not the bar code represents dark bars on a light background or light bars on a dark background. The decoder may be implemented either in hardware or as part of a program in a stored program general purpose computer. The signal processing approach taken generates gap sequence information from width sequence information to match predetermined gap sequence patterns. The method and apparatus of the present invention are also particularly amenable to independent creation of the gap sequences from three different techniques which are independent and which thus add robustness to the system. Lastly, the decoding method of the present invention takes advantage of a preprocessing function to remove any certain forms of noise that may be present in the scanned data.

Method and apparatus for bar code reading and decoding

A method and apparatus is provided for producing single width barcodes in a continuous, serpentine pattern. This pattern provides continuity of operation for laser marking instruments and thereby results in the formation of more uniform and higher quality barcode indicia. The use of a continuous serpentine pattern also increases the speed at which the code may be written onto a substrate. This marking method is particularly appropriate for use in marking a wide variety of materials including semiconductors, metals, plastics and ceramics.

Continuous barcode marking system

A single width bar code is appended with an end mark which includes a blank interval and a bar. The resulting bar code is bidirectional and inherently self clocking so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described are robust, reliable, and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

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Poughkeepsie, NY, United States of America

Mu-Yue Hsiao