Au Optronics Corporation

Mu-Lin Tung

Chao-Ching Hsu

Jen-Chieh Chen

Chung-Shen Cheng

Hsiao-Chung Cheng

Yi-Fan Lin

In one aspect of the invention, a source driver for driving a display panel to display an image data in an adaptive column inversion includes a data processing unit having a logic circuit adapted for determining N most-significant bits (MSBs) of image data signals of two neighboring data lines, such that when all of the N MSBs are equal to 1 or 0, the output of the logic circuit is 1, otherwise, the output of the logic circuit is 0, and a MUX coupled to the data processing unit and adapted for receiving a frame polarity control signal, FramePOL, and a pixel polarity control signal, XPOL, and selectively outputting the frame polarity control signal FramePOL when the output of the logic circuit is 1, or the pixel polarity control signal POL when the output of the logic circuit is 0, as a polarity control signal, POL.

Method and source driver for driving liquid crystal display

A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.

Display device, display device driving method and source driving circuit

The present invention in one aspect relates to a source driver for driving a display panel to display an image data in an adaptive column inversion. In one embodiment, the source driver includes a data processing unit having a logic circuit adapted for determining N most-significant bits (MSBs) of image data signals of two neighboring data lines, such that when all of the N MSBs are equal to 1 or 0, the output of the logic circuit is 1, otherwise, the output of the logic circuit is 0, and a MUX coupled to the data processing unit and adapted for receiving a frame polarity control signal, FramePOL, and a pixel polarity control signal, XPOL, and selectively outputting the frame polarity control signal FramePOL when the output of the logic circuit is 1, or the pixel polarity control signal POL when the output of the logic circuit is 0, as a polarity control signal, POL.

A level shift circuit includes a control logic circuit, a plurality of level shift output buffers and a plurality of charge sharing circuits. The control logic circuit receives input clock pulse signals and a charge sharing signal and acquires voltage level information of each received signal. Each output buffer amplifies a corresponding input clock pulse signal and determines whether to output a signal according to the acquired information of the charge sharing signal. Each charge sharing circuit determines whether to be turned on according to the acquired information of a corresponding input clock pulse signal. When a charge sharing circuit is turned on, the output terminal of a corresponding output buffer and a predetermined voltage level are coupled to each other by the charge sharing circuit, so as to perform the charge sharing operation. Furthermore, a corresponding liquid crystal display device and a corresponding charge sharing method are also provided.

Level shift circuit, liquid crystal display device and charge sharing method

A liquid crystal display includes a gate driver, a control circuit and a charge-sharing circuit. The control circuit provides a charge-sharing signal according to the parasitic capacitances at a first output end and a second output end in the gate driver. The charge-sharing circuit generates a third clock signal and a fourth clock signal by performing charge-sharing on a first clock signal and a second clock signal according to the charge-sharing signal. The third clock signal includes a signal falling edge which descends from a high level to a first level, and the fourth clock signal includes a signal falling edge which descends from the high level to a second level. The gate driver outputs a first gate driving signal and a second gate driving signal respectively at the first and the second output end according the third or the fourth clock signal.

Liquid crystal display with reduced image flicker and driving method thereof

A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

Liquid crystal display device capable of reducing image flicker and method for driving the same

A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

Growing community of inventors

Hsin-Chu, Taiwan

Mu-Lin Tung