Novatek Microelectronics Corp.

Mu-Jung Chen

Ren-Hong Luo

Yung-Cheng Lin

Shih-Chun Lin

Liang-Ting Kuo

Hsiang-Chi Li

Yan-Ting Wang

Chi-Chun Liao

Chu-Wei Hsia

Nan-Yuan Wang

A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.

Voltage regulator and method applied thereto

A low dropout voltage regulator, coupled to a load circuit receiving a clock signal, includes an amplifier; a power transistor comprising a control terminal, coupled to an output terminal of the amplifier; and a first terminal, coupled to a positive input terminal of the amplifier and the load circuit; and a control circuit, configured to control a current flowing through the power transistor in response to the clock signal.

Low dropout voltage regulator and related method

An electronic device capable of bandwidth compensation includes a register unit for storing a calibration code determined by performing an on-die termination (ODT) calibration process and a data receiving circuit, wherein the calibration code is utilized for controlling a termination resistance of an ODT unit. The data receiving circuit comprises a first control circuit coupled to the register unit and the active low-pass filter for generating a first control signal according to the calibration code stored in the register unit, the first control signal being utilized for adjusting a capacitance of a first feedback capacitor unit or a resistance of a first feedback resistor unit of an active low-pass filter.

Electronic device capable of bandwidth compensation and method thereof

A control circuit for a current switch of a current digital to analog converter (DAC) includes a first inverter, a second inverter, a first pull-low switch, a second pull-low switch and a timing synchronization circuit. The first inverter includes an input terminal and an output terminal. The second inverter includes an input terminal and an output terminal, wherein the input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled to the input terminal of the first inverter. The first pull-low switch is coupled to the input terminal of the first inverter. The second pull-low switch is coupled to the input terminal of the second inverter. The timing synchronization circuit is coupled to the first pull-low switch and the second pull-low switch.

Control circuit for current switch of current DAC

The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

Data serialization circuit

A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.

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Tainan, Taiwan

Mu-Jung Chen