Sitrus Technology Corporation

Marvell Asia Pte., Ltd.

Inphi Corporation

Mrunmay Talegaonkar

Michael Q Le

Jamal Riani

Yu Liao

Karthik S Gopalakrishnan

Aaron W Buchwald

Jorge Pernillo

Chang-Feng Loi

Belal Helal

Praveen Prabha

Junyi Sun

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Clock and data recovery devices with fractional-N PLL

A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency. In subsequent iterations, proportional feedback to the DCO of lower rate sums of symbol streams is combined with integral feedback of codes representing finer approximations of the unknown data frequency swept over successively narrowing bands, and the DCO is locked to the finest approximation that lies between consecutive codes corresponding to sums having opposite signs.

Referenceless frequency acquisition

An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

ADC having adjustable threshold levels for PAM signal processing

Growing community of inventors

Laguna Hills, CA, United States of America

Mrunmay Talegaonkar