Intel Corporation

Mrittika Ganguli

Abhirupa Layek

Edwin Verplanke

Rahul R Shah

David Sonnier

William G Burroughs

Shrikant M Shah

Sarita Maini

Bradley Chaddick

Ren Wang

Yipeng Wang

Priya Autee

Mohan J Kumar

Rajesh M Sankaran

Reshma Lal

Sujoy Sen

Stephen T Palermo

Sameh Gobriel

Murugasamy K Nachimuthu

Jr-Shian Tsai

Susanne M Balle

Thomas E Willis

Michael Orr

Yadong Li

Anjali Singhai Jain

Robert O Sharp

Niall D McDonnell

Narayan Ranganathan

Bradley A Burres

Nilesh K Jain

Brinda Ganesh

Jose Niell

Anjaneya Reddy Chagam Reddy

Gage Eads

Somnath Paul

Bruce Richardson

Chetan Hiremath

Muralidharan Sundararajan

Duane E Galbi

Neerav Parikh

Abhishek Khade

Valerie J Parker

Chih-Jen Chang

Hongjun Ni

Abhijit Davare

Sriram Kabisthalam Muthukumar

Anton Alexandrovich Sorokin

Desmond A Kirkpatrick

John Mangan

Niall Mcdonnell

Nupur Jain

Suvadeep Banerjee

Chenmin Sun

Praveen Mosur

Shaman Narayana

Jaykant B Timbadiya

Nalini Murari

Jeongnim Kim

Anandhi Jayakumar

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Dynamic load balancing for multi-core computing environments

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

Network layer 7 offload to infrastructure processing unit for service mesh

Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

Packet processing load balancer

Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

Hardware offload circuitry

Technologies for providing latency-aware consensus management in a disaggregated system include a compute device. The compute device includes circuitry to determine latencies associated with subsystems of the disaggregated system. Additionally, the circuitry is to determine, as a function of the determined latencies, a time period in which a configuration change to the disaggregated system is to reach a consistent state in the subsystems.

Technologies for providing latency-aware consensus management in a disaggregated architecture

Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.

5G network edge and core service dimensioning

Growing community of inventors

Chandler, AZ, United States of America

Mrittika Ganguli