Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Mrinal Kochar

Aaron Lee

Gautam Ashok Dusija

Abhijeet Bhalerao

Yew Yin Ng

Mikhail Palityka

Jian Feng Chen

Jianmin Huang

Dennis S Ea

Ivan Baran

Abhijeet Manohar

Piyush Girish Sagdeo

Jun Wan

Chris Avila

Deepak Raghu

Chris Nga Yee Avila

Yong Huang

Derek McAuley

Yingda Dong

Deepanshu Dutta

Zhenming Zhou

Dana Lee

Man Lung Mui

Seungpil Lee

Niles Yang

Venkatesh Ramachandra

Anubhav Khandelwal

Sahil Sharma

Jagdish Sabde

Pao-Ling Koh

Sagar Magia

Alexander Kwok-Tung Mak

Gulzar Ahmed Kathawala

Ashish Ghai

Yichao Huang

Matthew Davidson

Yong Peng

Yee Lih Koh

Yi-Chieh Chen

Rajan Paudel

Jia Ye

Cynthia Hua-Ling Hsu

Tosha Pandya

Anne Koh

Shmoolik Yosub

The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.

Error detection for training non-volatile memories

A method for writing data to a NAND flash memory is disclosed, having steps of writing a first set of data to a first memory block, writing a second set of data to a second memory block, writing a third set of data to a third memory block and writing a fourth set of data to a XNOR memory block.

Methods and operations using XNOR functions with flash devices and solid state drives

Systems and methods for storing data in a multi-level cell (MLC) flash memory are disclosed. One such data storage system has a data path with cascaded data access performance, including multiple storage portions having different data access speeds. A cascaded data path enables flash memory data access that has a more graceful degradation instead of an abrupt decrease in performance during operation.

Multi-level cell solid state device and method for transferring data between a host and the multi-level cell solid state device

Apparatuses, systems, methods, and computer program products are disclosed for changing storage parameters. An integrated circuit (IC) memory element receives a command to change a value of a parameter associated with the IC memory element. A parameter includes a setting for one or more storage operations of an IC memory element. An IC memory element receives one or more data sets with a command. A data set includes an identifier associated with a parameter to be changed and a new value for the parameter. Each of one or more data sets is received at a same data rate as a command. An IC memory element writes, for each of one or more data sets, a new value for a parameter to a storage location associated with the parameter.

Changing storage parameters

A system and method for operating a memory system includes receiving a first user data, writing the first user data to a first buffer, writing the first user data from the first buffer to a first selected memory location, writing the first user data from the first buffer into a second buffer when the first user data was successfully written to the first selected memory location. Data is retrieved from the first selected memory location and written into the first buffer. Data in the first buffer can be matched to the user data in the second buffer to confirm a successful storage of the first user data in the memory system. A previously stored user data can be retrieved from a third selected memory location and written into a third buffer when the previously stored user data was stored in the memory system before the first user data.

System, method and apparatus for preventing data loss due to memory defects using latches

A storage module and method for configuring the storage module with memory operation parameters are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a selection of one of a plurality of sets of memory operation parameters stored in the storage module and perform at least one of a read operation and a write operation on the memory in accordance with the selected set of memory operation parameters.

Storage module and method for configuring the storage module with memory operation parameters

Data that is initially stored in Single Level Cell (SLC) blocks is subsequently copied (folded) to a Multi Level Cell (MLC) block where the data is stored in MLC format, the data copied in a minimum unit of a fold-set, the MLC block including a plurality of separately-selectable sets of NAND strings, data of an individual fold-set copied exclusively to two or more word lines of an individual separately-selectable set of NAND strings in the MLC block.

Data folding in 3D nonvolatile memory

Systems and methods for partial bad block reuse may be provided. Data may be copied from a block of a first memory to a block of a second memory. A post write read error may be detected in a first portion the data copied to the block of the second memory without detection of a post write read error in a second portion of the data copied to the block of the second memory. The block of the second memory may be determined to be a partial bad block usable for storage in response to detection of the post write read error in the first portion of the data but not in the second portion of the data.

Partial bad block detection and re-use using EPWR for block based architectures

When the number of bad columns in a memory or plane is less than a threshold number then a first Error Correction Code (ECC) scheme encodes user data in first pages of a first size. If the number of bad columns is greater than the threshold number then a second ECC scheme encodes the user data in second pages of a second size that is smaller than the first size.

Bad column management in nonvolatile memory

Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.

Partially-bad block operation in 3-D nonvolatile memory

Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.

Non-volatile memory systems with multi-write direction memory units

Apparatus and method for performing a post-write read in a memory device are disclosed. A memory device may include 3-dimensional memory, with the wordlines in a memory block each having multiple strings. Periodically, the memory device may analyze the wordlines for defects by performing a post-write read on a respective wordline and analyzing the read data to determine whether the respective wordline is defective. Rather than reading all of the strings for the respective wordline, less than all of the strings (such as only one of the strings) for the respective wordline are read. In this way, determining whether the respective wordline in 3-dimensional memory may be performed more quickly.

Enhanced post-write read for 3-D memory

Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.

Word line look ahead read for word line to word line short detection

A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.

Read disturb detection in open blocks

Methods are provided for programming multi-level non-volatile memory cells, the multi-level non-volatile memory cells accessible by a plurality of word lines. The methods include using a four-pass programming technique to program a block of the multi-level non-volatile memory cells, detecting a power cycle before completing programming of the block of the multi-level non-volatile memory cells, and upon power-up initialization, resuming programming on the block of the multi-level non-volatile memory cells.

Initialization techniques for multi-level memory cells using multi-pass programming

Growing community of inventors

San Jose, CA, United States of America

Mrinal Kochar