Advanced Micro Devices Corporation

Freescale Semiconductor,inc.

Samsung Electronics Co., Ltd.

Mrinal Bose

Jayanta Bhadra

Hillel Miller

Edward L Swarthout

James Longino

Yaniv Fais

Sharon Goldschlager

Amit Hermony

Prashant U Naphade

Ekaterina A Trofimova

Pankaj Sharma

Robert S Slater

Laxmi Narayana Yakkala

Kenneth G Davis

A method for minimizing a test set for optimal coverage is disclosed. The method includes generating a first test set which is both an empty and minimal test set. Then, generating a second test set with a predetermined number of tests. Further, partitioning the second test set into a control test set and an experiment test set. Subsequently, providing a list of tests for coverage by merging the control test set with the first test set to form a merged list of sets.

Method and apparatus for obtaining a maximally compressed verification test set

An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device.

Video and image compression based on position of the image generating device

A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.

Trace reconstruction for silicon validation of asynchronous systems-on-chip

An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Stream based stimulus definition and delivery via interworking

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Austin, TX, United States of America

Mrinal Bose