Qualcomm Incorporated

Mriganka Mondal

Moinul H Khan

Martin Renschler

Hee Jun Park

Ronald Alton

Gheorghe Calin Cascaval

Idreas Mir

Mehrad Tavakoli

Steven S Thomson

Young Hoon Kang

Raghavendra Nagaraj

Nishant Hariharan

Rajiv Vijayakumar

Maurice Ribble

An apparatus is configured to render graphics content to reduce latency of the graphics content. The apparatus includes a display configured to present graphics content including a first portion corresponding to an area of interest and further including a second portion. The apparatus further includes a fovea estimation engine configured to generate an indication of the area of interest based on scene information related to the graphics content. The apparatus further includes a rendering engine responsive to the fovea estimation engine. The rendering engine is configured to perform a comparison of a first result of an evaluation metric on part of the area of interest with a second result of the evaluation metric with another part of the area of interest. The rendering engine is further configured to render the graphics content using predictive adjustment to reduce latency based on the comparison.

Scene-based foveated rendering of graphics content

Systems, methods, and computer programs are disclosed for reducing memory bandwidth via multiview compression/decompression. One embodiment is a compression method for a multiview rendering in a graphics pipeline. The method comprises receiving a first image and a second image for a multiview rendering. A difference is calculated between the first and second images. The method compresses the first image and the difference between the first and second images. The compressed first image and the compressed difference are stored in a memory. The compressed first image and the compressed difference are decompressed. The second image is generated by comparing the first image to the difference.

Systems and methods for reducing memory bandwidth via multiview compression/decompression

Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

CPU/GPU DCVS co-optimization for reducing power consumption in graphics frame processing

Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.

System and apparatus for consolidated dynamic frequency/voltage control

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San Diego, CA, United States of America

Mriganka Mondal