Purdue Research Foundation

International Business Machines Corporation

Mrigank Sharad

Kaushik Roy

Phillip John Restle

Alan J Drake

Aditya Bansal

Thomas J Bucelot

David W Shan

An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.

Electronic comparison systems

A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.

Clock buffers with pulse drive capability for power efficiency

A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.

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West Lafayette, IN, United States of America

Mrigank Sharad