Apple Inc.

Mridul Agarwal

Kulin N Kothari

Gideon N Levinsky

Richard F Russo

Pradeep Kanapathipillai

Christopher M Tsay

Stephan G Meier

Charles E Tucker

Yuan C Chou

Lior Zimet

Aditya Kesiraju

James Vash

Tal Kuzi

Shih-Chieh Wen

Tyler J Huberty

Deepankar Duggal

Nikhil Gupta

Jeffrey E Gonion

Yanran Yang

Brian Robert Mestan

John H Kelm

Rajat Goel

Jeff Gonion

Debasish Chandra

Sean M Reynolds

Haoyan Jia

Gerard Richard Williams

Sandeep Kumar Gupta

Wei-Han Lien

John D Pape

Rohit Kumar

Francesco Spadini

Amit Kumar

Niket K Choudhary

Deepak Limaye

Douglas C Holman

Eric Jason Furbish

Harsha Krishnamurthy

Peter G Soderquist

Vivek Venkatraman

Viney Gautam

Chandan Shantharaj

Muthukumaravelu Velayoudame

Shyam Sundar Balasubramanian

Stephen G Meier

Christopher S Thomas

Sahil Kapoor

Chang Xu

Pankaj Lnu

Zhaoming Hu

Madhu Sudan Hari

A reservation station that includes primary and secondary storage circuits is disclosed. The primary storage circuit may include multiple full entries, while the secondary storage circuit includes multiple store-data entries. A given store-data entry of the multiple store-data entries stores a subset of the information stored in a given full entry of the multiple full entries. In response to a determination that a store address associated with a particular store operation, stored in particular full entry of the multiple full entries, has been available for use for a threshold number of cycles without store data associated with the particular store operation being available for use, a control circuit may transfer the particular store operation to a particular store-data entry of the multiple store-data entries.

Reservation station with primary and secondary storage circuits for store operations

Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

DSB operation with excluded region

An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Scalable interrupts

An apparatus includes a cache memory circuit, a prefetcher circuit, and a prefetch deny list circuit, including a plurality of entries, may be included. The cache memory circuit may be configured to store information retrieved from a lower-level memory. The prefetcher circuit may be configured to generate a prefetch request for a particular prefetch address. The prefetch deny list circuit may be configured to allocate, in response to an indication from the cache memory circuit that a previously prefetched address went unused, a given entry, of the plurality of entries, for the previously prefetched address. The prefetch deny list circuit may be further configured to determine whether a particular address for a particular prefetch request corresponds to an active one of the plurality of entries. In response to a determination that a particular active entry corresponds to the particular address, prefetch deny list circuit may deny the particular prefetch request.

Deny list for a memory prefetcher circuit

A livelock resolution circuit may be used to detect and remove a livelock from a processor. The livelock resolution circuit may use a counter, whose value may be reset or incremented depending on a status of a retire pointer in a reorder buffer circuit (ROB). When the retire pointer fails to move from one operation to another over a period of time, the value in the counter may continuously increment to exceed a threshold, indicating that the period of time elapses without a successful retirement of an operation from the ROB. Thus, the livelock resolution circuit may determine that a livelock occurs. To remove the livelock, the livelock resolution circuit may involve a single-step operational mode, where the livelock resolution circuit may demand only one operation (or microoperation) to be executed at each step. As a result, the operation may be retired and the livelock may be removed.

Livelock detection and resolution using oldest operation tracking

An apparatus includes a cache memory circuit, and a hierarchal store queue circuit that further includes a primary queue and a secondary queue. The hierarchal store queue circuit may be configured to write incoming store requests to the primary queue in response to the primary queue currently having capacity, and to write incoming store requests to the secondary queue in response to the primary queue currently not having capacity. The hierarchal store queue circuit may be further configured to commit store requests to the cache memory circuit from the primary queue but not from the secondary queue. In response to a determination that the primary queue currently has capacity, the hierarchal store queue circuit may perform a transfer of at least one store request from the secondary queue to the primary queue.

Hierarchical store queue circuit

A system may include multiple processors. One of the processors may receive an indication of a data synchronization barrier (DSB) instruction in another processor that follows a translation look-ahead buffer invalidate (TLBI) instruction to invalidate an entry of a translation look-ahead buffer. The processor may determine whether instructions are pending in the processor for which the virtual addresses used for memory accesses have been translated to physical addresses before receiving the DSB indication. If there are such pending instructions, the processor may provide, after these instructions retire, an indication to the other processor as a response to the DSB indication.

Processing of data synchronization barrier instructions

Techniques are disclosed relating to load value prediction. In some embodiments, a processor includes learning table circuitry that is shared for both address and value prediction. Loads may be trained for value prediction when they are eligible for both value and address prediction. Entries in the learning table may be promoted to an address prediction table or a load value prediction table for prediction, e.g., when they reach a threshold confidence level in the training table. In some embodiments, the learning table stores a hash of a predicted load value and control circuitry uses a probing load to retrieve the actual predicted load value for the value prediction table.

Shared learning table for load value prediction and load address prediction

A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.

Processing of synchronization barrier instructions

In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

Decoupling atomicity from operation size

A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

Early load execution via constant address and stride prediction

A method and system for compressing and decompressing data is disclosed. A compression command may initiate the prefetching of first data, which may be stored in a first buffer. Multiple words of the first data may be read from the first buffer and used to generate a plurality of compressed packets, each of which includes a command specifying a type of packet. The compressed packets may be combined into a group and multiple groups may be combined and stored in a second buffer. A decompression command may initiate the prefetching of second data, which is stored in the first buffer. A portion of the second data may be read from the first buffer and used to generate a group of compressed packets. Multiple output words may be generated dependent upon the group of compressed packets.

Hardware compression and decompression engine

Growing community of inventors

Sunnyvale, CA, United States of America

Mridul Agarwal