Intel Corporation

Mozhgan Mansuri

Bryan K Casper

James E Jaussi

Frank Patrick O'Mahony

Stephen R Mooney

Aaron K Martin

David Stewart Dunning

Ganesh Balamurugan

Roger K Cheng

James A McCall

Matthew B Haycock

Joseph T Kennedy

Navneet Dour

Ajay Balankutty

Dave Dunning

Randy R Mooney

Kuan Zhou

Sridhar Tirumalai

Krishnamurthy Venkataramana

Alex Thomas

Hari Venkatramani

Quoc Nguyen

Rajesh Inti

Timothy Hollis

Sujit Sharan

Debendra Mallik

Srinivas V Pietambaram

Kristof Darmawikarta

Rahul N Manepalli

Christopher P Mozak

Zhichao Zhang

Brandon C Marin

Gang Duan

Sai Vadlamani

Xiaoqian Li

Bai Nie

Jason M Gamba

Sameer Paital

Arnab Sarkar

Sami Hyvonen

Harishankar Sridharan

Divya Pratap

Kenneth Brown

Suresh V Pothukuchi

Kemal Aygün

Hsien-Pao Yang

Hariprasath Venkatram

Sudip Shekhar

Mohammed G Mostofa

Pavan Kumar Kappagantula

Susnata Mondal

Susheel Jadhav

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

An integrated circuit having a transmission-line-based resonant clock distribution network for distributing a clock signal to one or more nodes, the integrated circuit including a transmission-line-based resonant network formed by one or more clock distribution units. Each clock distribution unit includes a transmission line segment having first and second ends and a resonant circuit connected to the transmission line segment at a position equidistant from the first end and the second end, where the resonant circuit includes an inductor connected in parallel with a capacitor such that the resonant circuit, along with the transmission line segment, collectively has a resonant frequency about a frequency of the clock signal.

Transmission-line-based resonant quadrature clock distribution with harmonic filtering

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)

Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Systems, methods, and apparatuses for stacked memory

An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Dual power I/O transmitter

Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

Reconfigurable clocking architecture

Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.

Clock calibration using asynchronous digital sampling

An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.

On-die all-digital delay measurement circuit

Growing community of inventors

Hillsboro, OR, United States of America

Mozhgan Mansuri