Spin Memory, Inc.

Crocus Technology Inc.

Crocus-technology Sa

Avalanche Technology, Inc.

Integrated Silicon Solution Incorporated

Mourad El Baraji

Neal Berger

Marcin Gajek

Kadriye Deniz Bozdag

Benjamin S Louie

Michail Tzoufras

Lester Crudele

Eric Ryan

Virgile Javerliac

Bertrand Francis Cambou

Amitay Levi

Daniel L Hillman

Susmita Karmakar

Barry Hoberman

Thinh Tran

Lucien Lombard

Guillaume Prenat

Erwan Gapihan

Guy Yuen

Lucian Prejbeanu

Ricardo Alves Ferreira Costa E Sousa

Benjamin Stanley Louie

Lester M Crudele

An apparatus includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a second MTJ having a second magnetic characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The first magnetic characteristic is based on a first magnetic anisotropy and a first offset field on a first storage layer of the first MTJ. The second magnetic characteristic is based on a second magnetic anisotropy and a second offset field on a second storage layer of the second MTJ, The apparatus further includes a metallic separator coupling the first MTJ with the second MTJ, wherein the first MTJ and the second MTJ are arranged in series.

Systems and methods utilizing serial and parallel configurations of magnetic memory devices

A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.

Memory array with individually trimmable sense amplifiers

An memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A first circuit provides a first voltage on an addressed bit line of the plurality of bit lines during a write cycle, wherein the addressed bit line corresponds to an addressed memory cell. A second circuit provides a second voltage on remainder bits lines of the plurality of bit lines, wherein the second voltage is operable to be applied to the common source line, via the remainder bit lines, during the write cycle.

Memory array with horizontal source line and a virtual source line

The present invention is directed a method for programming multiple memory cells connected to a common word line to different resistance regimes. Each cell includes a bipolar switching memory element and an access transistor coupled in series between first and second conductive lines. The memory element and access transistor are disposed adjacent to the first and second conductive lines, respectively. The method includes the steps of applying a first voltage to the common word line to program a first group of memory cells to a first resistance regime; and after the first group of memory cells is programmed to the first resistance regime, programming a second group of memory cells to a second resistance regime by raising the potential of second conductive lines connected to the first group of memory cells to a second voltage and raising the first voltage of the common word line to a third voltage.

Fast programming of magnetic random access memory (MRAM)

Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Read-out techniques for multi-bit cells

Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Multi-bit cell read-out techniques

Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.

Method of reading data from a memory device using multiple levels of dynamic redundancy registers

A memory cell apparatus is provided. The apparatus comprises two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ having a second magnetic characteristic and a second electrical characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The apparatus further comprises a transistor having three terminals, where the first MTJ is coupled to a first terminal of the three terminals and a metallic separator coupling the first MTJ with the second MTJ. The first MTJ and the second MTJ are arranged in series.

Systems and methods utilizing serial configurations of magnetic memory devices

A memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A sacrificial circuit element is coupled to a sacrificial bit line, coupled to the common word line and coupled to the common source line, wherein the sacrificial circuit element is operable to provide a desired voltage to the common source line wherein the desired voltage originates from the sacrificial bit line.

Memory array with horizontal source line and sacrificial bitline per virtual source

A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells.

Perpendicular source and bit lines for an MRAM array

Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (e1 register) is couple to the memory bank. The e1 register may store data words that have failed verification or have not been verified. The e1 register may transfer data words to another dynamic redundancy register (e2 register). The e1 register may transfer data words that have failed to write to a memory bank after a predetermined number of re-write attempts. The e1 register may also transfer data words upon power down.

Device with dynamic redundancy registers

Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes an in-plane polarization magnetic layer and a perpendicular MTJ in conjugation with a alternating current precharge and a programming current pulse that comprises an alternating perturbation frequency and a direct current.

AC current pre-charge write-assist in orthogonal STT-MRAM

A magnetic storage device is provided. The magnetic storage device comprises a magnetic memory cell, which includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ has a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic. The magnetic memory cell further comprises a bottom electrode and a top electrode, wherein the two or more MTJs are arranged between the top and bottom electrode in parallel with respect to each other. The magnetic storage device further comprises readout circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell and write circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell.

Systems and methods utilizing parallel configurations of magnetic memory devices

Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device also utilizes an external magnetic field generator, thereby allowing efficient writing of the bit without a concomitant increase in read disturb.

Growing community of inventors

Fremont, CA, United States of America

Mourad El Baraji