International Business Machines Corporation

Mounir Meghelli

Daniel Joseph Friedman

Russell Alan Budd

Jason Scott Orcutt

Jean-Olivier Plouchart

John Francis Bulzacchelli

Sergey Vladimirovich Rylov

Timothy O Dickson

Hayden C Cranford, Jr

Thomas Helmut Toifl

Jonathan E Proesel

Daniel Mark Dreps

Anthony Richard Bonaccio

Steven John Baumgartner

David W Siljenberg

Timothy Clyde Buchholtz

Charles Porter Geer

Dana Marie Woeste

Gautam Gangasani

Arvind Kumar

Alexander V Rylyakov

Joshua M Rubin

Keith Aelwyn Jenkins

Steven Lorenz Wright

Michael Anthony Sorna

Jose A Tierno

Troy James Beukema

Herschel Akiba Ainspan

Matthew James Paschal

Hyung-Min Lee

John Farley Ewen

Steven John Zier

Matthew B Baecher

Benjamin D Parker

Zeynep Toprak-Deniz

Guanghua Shu

Trushil N Shah

James F Buckwalter

Glenn E R Cowan

Azita Emami-Neyestanak

Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

Interconnection structures for high bandwidth data transfer

Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

Transmitter with fully re-assignable segments for reconfigurable FFE taps

A single-ended inter-chip data transmission system and a single-ended inter-chip data reception system are provided for processing data. A controlled Hamming weight parallel data encoder at a transmitter device accepts N data bits with an arbitrary Hamming weight as input and generates M data bits with a controlled Hamming weight as output, wherein M is greater than N. A transmission circuit provides a time-aligned transmission of the controlled Hamming weight encoded data across a single-ended data bus.

Inter-chip data transmission system using single-ended transceivers

A neural signal recording device includes a scan-mode circuit and a read-mode circuit. The scan-mode circuit detects neural spike activity within any M groups of electrodes selected from a total of N electrodes that are coupled to a brain. The read-mode circuit then records all neural spike signals present within any one of the M groups of electrodes where the neural spike activity is detected by the scan-mode circuit, whereby less than N electrodes are recorded at any one time by the neural signal recording device.

Neural spike scanning for high-density implantable neural recording systems

A serial transmitter that outputs one symbol every unit interval (UI) from a data source is presented. The serial transmitter includes a serial output port that outputs one symbol every unit interval (UI) from a data source. The serial transmitter also includes a plurality of driver segments that jointly drive the serial output port. Each driver segment is configured to use one of N phases of a sampling clock to serialize and transmit data from the data source. Different sets of the driver segments are configured to use different phases of the sampling clock for serializing and transmitting data, the sampling clock being a half-rate clock having a period of two UI.

Serial transmitter with feed forward equalizer

Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

High speed DFEs with direct feedback

A timing error detection circuit for calibrating a serial transmitter is disclosed. The circuit includes a data source configured to provide data for serial transmission and a clock source configured to produce N versions of a sampling clock that are at N different phases of the sampling clock. The detection circuit has a first sampler configured to sample the data source by using a first phase of the sampling clock to generate a first sampled signal and a second sampler configured to sample the data source by using a second phase of the sampling clock to generate a second sampled signal. The detection circuit also includes a first comparator configured to compare the first and second sampled signals to generate a difference signal and a first low-pass filter configured to filter the difference signal to generate an average difference voltage. A second comparator in the detection circuit is configured to compare the average difference voltage with a reference voltage.

Serial transmitter with feed forward equalizer and timing calibration

Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.

Calibration of sampling phase and aperature errors in multi-phase sampling systems

A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

System and method for latency reduction in speculative decision feedback equalizers

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Tarrytown, NY, United States of America

Mounir Meghelli