Cadence Design Systems, Inc.

Ciena Corporation

Mouna Safi-Harab

Xiaobin Yuan

Naim Ben-Hamida

Sadok Aouini

Soheyl Ziabakhsh Shalmani

Aida Varzaghani

Hiu Ming Lam

Irina Gavshina

Dimitri Loizos

A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.

Successive approximation register based time-to-digital converter using a time difference amplifier

In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.

Systems and methods for communicating clock signals

The present embodiments relate generally to data communications, and more particularly to systems including high-speed serializer-deserializer circuits having TCOILs. One or more embodiments are directed to a four-terminal TCOIL structure that consumes the same amount of area on a chip as a traditional three-terminal structure, while providing more bandwidth and less reflection and group delay variation.

Compact four-terminal TCOIL

Growing community of inventors

Montreal, Canada

Mouna Safi-Harab