Megica Corporation

Icometrue Company Ltd.

Megic Corporation

Other

Qualcomm Incorporated

Megit Acquisition Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Magic Corporation

M. S. Lin

United Microelectronics Corp.

Etron Technology, Inc.

Stembios Technologies, Inc.

Marvell Semiconductor, Inc.

Megit Acquistion Corp.

Mecic Corporation

Mou-Shiung Lin

Jin-Yuan Lee

Ching-Cheng Huang

Chien-Kang Chou

Chiu-Ming Chou

Hsin-Jung Lo

Shih-Hsiung Lin

Ying-Chih Chen

Ke-Hung Chen

Ming-Ta Lei

Bryan Peng

Chuen-Jye Lin

Ching-San Lin

Ping-Jung Yang

Shun-Liang Hsu

Wen-Chieh Lee

Yi-Cheng Liu

Mark Chou

Michael Chen

Tah-Kang Joseph Ting

Ming-Dar Lei

Te-Sheng Liu

Huei-Mei Yen

Sehat Sutardja

Mong-Song Liang

Albert M Wu

James Han Wang

Chue-San Yoo

Steve K Chen

Yun Yen

Han-Liang Tseng

Gu-Yeon Wei

Jin Yuan Lee

Shih Hsiung Lin

Chien Kang Chou

Jin-Yuen Lee

Vang Cheong

Chun-Yi Shi

Jin-Yaun Lee

Shung-Liang Hsu

Shih-Hsiung Lin, I

A micro heat transfer component includes a bottom metal plate; a top metal plate; a plurality of sidewalls each having a top end joining the top metal plate and a bottom end joining the bottom metal plate, wherein the top and bottom metal plates and the sidewalls form a chamber in the micro heat transfer component; a plurality of metal posts in the chamber and between the top and bottom metal plates, wherein each of the metal posts has a top end joining the top metal plate and a bottom end joining the bottom metal plate; a metal layer in the chamber, between the top and bottom metal plates and intersecting each of the metal posts, wherein a plurality of openings are in the metal layer, wherein a first space in the chamber is between the metal layer and bottom metal plate and a second space in the chamber is between the metal layer and top metal plate; and a liquid in the first space in the chamber.

Micro heat pipe for use in semiconductor IC chip package

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

Logic drive using standard commodity programmable logic IC chips

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equal to 512.

Logic drive based on multichip package using interconnection bridge

A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

Vertical interconnect elevator based on through silicon vias

A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation.

Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits

A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling to the first latch node, a sixth terminal coupling to a third output point of the memory cell, and a third gate terminal for controlling coupling between the first latch node and the third output point of the memory cell.

Multi-output look-up table (LUT) for use in coarse-grained field-programmable-gate-array (FPGA) integrated-circuit (IC) chip

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Logic drive based on standardized commodity programmable logic semiconductor IC chips

A connector may include: a first substrate having a top surface, a bottom surface opposite to the top surface of the top substrate and a side surface joining an edge of the top surface of the first substrate and joining an edge of the bottom surface of the first substrate; a second substrate having a top surface, a bottom surface opposite to the top surface of the second substrate and a side surface joining an edge of the top surface of the second substrate and joining an edge of the bottom surface of the second substrate, wherein the side surface of the second substrate faces the side surface of the first substrate, wherein the top surfaces of the first and second substrates are coplanar with each other at a top of the connector and the bottom surfaces of the first and second substrates are coplanar with each other at a bottom of the connector; and a plurality of metal traces between, in a first horizontal direction, the side surfaces of the first and second substrates, wherein each of the plurality of metal traces has a top end at the top of the connector and a bottom end at the bottom of the connector.

3D chip package based on vertical-through-via connector

Logic drive based on standard commodity FPGA IC Chips using non-volatile memory cells

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Logic drive based on standard commodity FPGA IC chips

Growing community of inventors

Hsin-Chu, Taiwan

Mou-Shiung Lin