Intel Corporation

Moty Mehalel

Vivek K De

Muhammad M Khellah

George Shchupak

Tsvika Kurts

DiaaEldin S Khalil

Alexander Gendler

John H Crawford

Julius Yuli Mandelblat

DiaaEidin S Khalil

A register file employing a shared supply structure to improve the minimum supply voltage.

Circuits and methods for reducing minimum supply for register file cells

Methods and apparatus to track the health of integrated circuit structures are described. In an embodiment, a counter may be updated when the status of a portion of a storage unit (e.g., a cache) transitions to a defective status (e.g., as determined by reference to one or more corresponding status bits). The value stored in the counter may be compared with a threshold value, e.g., to generate a signal that is indicative of whether the threshold value has been exceeded. Other embodiments are also described.

Tracking health of integrated circuit structures

Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.

Method and apparatus of reporting memory bit correction

Setting a minimum operating voltage (Vcc min) of the cache to a voltage value at which the number of cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining cells continue to function correctly at the voltage value chosen for Vcc min, and compensating for errors produced by memory cells in the cache that fail when operated at the voltage value chosen for Vcc min.

Lowering voltage for cache memory operation

Embodiments of the present invention relate to a circuit that varies the delay time of a clock signal in response to a frequency of the clock signal. The circuit may include a sensor and a delay circuit. The sensor may output a determination of the frequency of the clock signal. The delay time of the delay circuit may be responsive to the determination of a frequency of the clock signal. Accordingly, when the frequency of a clock signal varies, a delay of that clock signal can be varied to accommodate for the change in frequency.

Adaptive delay of timing control signals

An integral modular cache. One embodiment includes a processor portion and a cache memory portion. The cache memory portion includes an array portion having tag logic and a set portion. The array portion extends along substantially all of a first axis of the processor. Control logic is to receive a cache size indicator and is capable of operating the cache with the one set portion or with additional set portions.

Integral modular cache for a processor

A short write test circuit and mode. One disclosed apparatus includes a memory cell that is connected to a first bit line and a second bit line. The short write test circuit causes a short write having a programmable duration to stress the memory cell.

Short write test mode for testing static memory cells

A four transistor memory cell having a pair of cross coupled transistors and a pair of pass gates is disclosed. The four transistor memory cell is refreshed by charge transfer between the bit lines the internal nodes during bit line precharge.

Growing community of inventors

Haifa, Israel

Moty Mehalel