Kabushiki Kaisha Toshiba

Ebara Corporation

Toshiba Memory Corporation

Motoyuki Sato

Katsuyuki Sekine

Akio Kaneko

Seiji Inumiya

Kazuhiro Eguchi

Hiroshi Tomita

Soichi Nadahara

Kenya Ito

Norio Kimura

Kyoichi Suguro

Masatoshi Yoshikawa

Yoshiaki Asao

Takeshi Watanabe

Minoru Amano

Yoshitaka Tsunashima

Gaku Minamihaba

Kazuaki Nakajima

Yukiteru Matsui

Tomohiro Saito

Keisuke Nakatsuka

Junji Kunisawa

Tomonori Aoyama

Yasunobu Onishi

Akira Fukunaga

Masako Kodera

Eishi Shiobara

Hisataka Hayashi

Tokuhisa Ohiwa

Mitsuhiko Shirakashi

Kazumasa Sunouchi

Takashi Obara

Masayoshi Iwayama

Takashi Nakazawa

Yasuhiko Sato

Hajime Eda

Junko Ohuchi

Yuuki Inoue

According to one embodiment, a magnetic storage device includes memory cells, wherein each of the memory cell includes: a wiring including a first ferromagnetic layer and a first nonmagnetic layer disposed on the first ferromagnetic layer; a magnetoresistive effect element including a second ferromagnetic layer disposed on the first nonmagnetic layer, a third ferromagnetic layer, and a second nonmagnetic layer disposed between the second and the third ferromagnetic layer; a first transistor having a first terminal connected to the first ferromagnetic layer, and a second terminal connected to a source line; and a second transistor having a first terminal connected to the third ferromagnetic layer, and a second terminal connected to a bit line.

Magnetic storage device with a wiring having a ferromagnetic layer

According to one embodiment, a memory device includes a spin transfer torque magnetoresistive element including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a temperature detecting unit detecting an ambient temperature of the magnetoresistive element, and a write voltage generating unit generating a write voltage for the magnetoresistive element in accordance with the temperature detected by the temperature detecting unit.

Memory device

According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.

Method of manufacturing nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer.

Nonvolatile semiconductor memory device and method of manufacturing

According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, a first charge trap layer on the interface insulating layer, and a second charge trap layer on the first charge trap layer, and a trap level of the second charge trap layer is lower than a trap level of the first charge trap layer.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.

Resistance change memory and method of manufacturing the same

According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a first floating gate electrode on the tunnel insulating film, an inter-floating gate insulating film on the first floating gate electrode, a second floating gate electrode on the inter-floating gate insulating film, an inter-electrode insulating film on the second floating gate electrode, and a control gate electrode on the inter-electrode insulating film. The inter-floating gate insulating film includes a main insulating film, and a first fixed charge layer between the main insulating film and the second floating gate electrode and having negative fixed charges.

Semiconductor device with fixed charge layers

According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:

CMOS device fabrication method with PMOS interface insulating film formed concurrently with sidewall insulating film

A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiOfilm, a film containing SiOas a main component and at least one of Hf and Zr, a film containing SiOas a main component and N, a film containing SiOas a main component, Hf and N, a film containing SiOas a main component, Zr and N, or a film containing SiOas a main component, Hf, Zr and N.

Semiconductor apparatus and method of manufacturing the semiconductor apparatus

Semiconductor apparatus having a semicondutor element with a high dielectric constant film

A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.

Method of manufacturing semiconductor device

A manufacturing method of a semiconductor device disclosed herein, comprises: forming a silicate film containing metal on a substrate; and introducing nitrogen and deuterium into the silicate film by using NDgas.

Semiconductor device and manufacturing method of the same

Growing community of inventors

Yokohama, Japan

Motoyuki Sato