Hitachi, Ltd.

Other

Hitachi Maxell, Limited

Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Maxwell, Ltd.

Hitachi Computer Peripherals Co., Ltd.

Hitachi Displays, Ltd.

Nippon Hoso' Kyokai

Hitachi, Lt.

Motoyasu Terao

Harukazu Miyamoto

Hiroyuki Minemura

Akemi Hirotsune

Tetsuya Nishida

Yasushi Miyauchi

Hirofumi Sukeda

Tetsuo Andou

Keikichi Andoo

Makoto Miyamoto

Yumiko Anzai

Junko Ushiyama

Norikatsu Takaura

Hideyuki Matsuoka

Shinkichi Horigome

Hiroki Yamamoto

Ken Takahashi

Satoru Hanzawa

Tsuyoshi Toda

Hideki Saga

Masatoshi Ohtake

Toshimichi Shintani

Kenzo Kurotsuchi

Takashi Naito

Fumiyoshi Kirino

Masahiro Ojima

Kazuo Shigematsu

Sumio Hosaka

Eiji Koyama

Takashi Namekawa

Kiyoo Itoh

Takeshi Sakata

Norio Ohta

Kyoko Kojima

Takeshi Maeda

Yoshio Taniguchi

Hitoshi Kume

Hisataka Sugiyama

Yoshitaka Sasago

Seiji Yonezawa

Nobuyuki Inaba

Takashi Naitou

Yuko Tsuchiya

Kiyoshi Matsumoto

Takahiro Morikawa

Keikichi Ando

Riichiro Takemura

Nozomu Matsuzaki

Yuichi Matsui

Masaharu Kinoshita

Yoshinori Miyamura

Yasushi Tomioka

Tomonori Sekiguchi

Takeshi Shimano

Toshimitsu Kaku

Nobuhiro Tokushuku

Yoshihisa Fujisaki

Shuji Imazeki

Yukio Fukui

Makoto Saen

Yasutaka Suzuki

Reiji Tamura

Munehisa Mitsuya

Mitsuhide Miyamoto

Naoki Yamamoto

Tetsuo Nakazawa

Masahiko Takahashi

Akira Gotoh

Yasuo Imanishi

Tsutomu Fujita

Minoru Ogushi

Ryo Suzuki

Hiroyuki Suzuki

Shigeru Nakamura

Tadashi Ikeda

Takuya Matsumoto

Akira Arimoto

Masaaki Futamoto

Takeo Shiba

Seiichi Mita

Yoshinobu Kimura

Hideaki Yamamoto

Yoshito Tsunoda

Kimio Tatsuno

Tadaaki Hirai

Hiroyuki Kimura

Kunikazu Ohnishi

Eiichi Maruyama

Naohiko Irie

Takeshi Nakao

Akio Shima

Keiichi Shidara

Masaaki Kurebayashi

Mitsuharu Tai

Fumio Kugiya

Toshio Niihara

Toshimasa Kamisada

Shinichi Nakatsuka

Masuo Kasai

Yoshihiro Hamakawa

On an insulating film () in which a plug () as a lower electrode is embedded, a laminated layer pattern of an insulating film () made of tantalum oxide, a recording layer () made of Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced and an upper electrode film () made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film () between the recording layer () and the plug (), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer () can be achieved. Further, by using the Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced as the recording layer (), the difference in work function between the insulating film () and the recording layer () is increased, and the programming voltage of the phase change memory can be reduced.

Semiconductor device

On the same semiconductor substrate, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layerstoring a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layeris made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Method of manufacturing non-volatile memory module

A recording layermade of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layerpositioned on a lower electrode TP side of the recording layeris higher than the corresponding concentration of a second layerpositioned on an upper electrodeside. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

Semiconductor integrated circuit device

A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.

Semiconductor device with recording layer containing indium, germanium, antimony and tellurium

A recording medium including a plurality of recording layers, including: an optional first recording layer on which a light spot at a diffraction limit is formed; and a second recording layer on which a mark string pattern is formed, said second recording layer being different from said first recording layer, wherein when said mark string pattern is formed on a light receiving plane, while information of said first recording layer is reproduced, assuming that an optical distance between said first and second recording layers is dm, an optical distance d between optional two recording layers among a plurality of said recording layers is different from said dm.

Three-dimensional recording and reproducing apparatus

Recording information is disclosed in which an information recording medium is irradiated with a recording energy beam that is power-modulated into at least a record power level and a record-ready power level lower than the record power level. The information is recorded on the recording medium in the form of length and interval of a mark portion. When forming a mark portion of a predetermined length, the radiation energy of the energy beam is increased as compared with when forming a mark portion of a different length before or after the first pulse of an energy beam pulse train including at least a pulse for forming the mark portion.

Information recording method and apparatus with suppressed mark edge jitters

Semiconductor device having user field and vendor field

Growing community of inventors

Hinode, Japan

Motoyasu Terao