Fujitsu Corporation

Other

Fujitsu Vlsi Limited

Fujitsu Limited & Fujitsu Vlsi Limited

Motoo Nakano

Takashi Iwai

Nobuo Sasaki

Haruhisa Mori

Hiroshi Nomura

Toshimi Ikeda

Masaya Katayama

Fumihiko Inoue

Masahiro Kuwamura

Junichi Ishikawa

George J Collins

Kunihiko Wada

Tetsuro Tamura

Hajime Kamioka

Masao Yamada

Yasuo Kobayashi

Akira Takazawa

Takashi Matsumoto

Ryoichi Mukai

Yoshinobu Ono

Mikio Takagi

Noriaki Sato

Tsutomu Ogawa

Ryoiku Tohgei

Takashi Igarashi

Masako Iizuka

Masanao Hotta

Microstructures, including a plurality of spaced structural members which are bendable under an external force, undergo a treating method using a first treating liquid, to prevent permanent deformation, by removing the microstructure from the first treating liquid to an environment having a pressure less than atmospheric pressure; or moving the microstructure from the first treating liquid to a second treating liquid having a smaller surface tension than the first treating liquid, and then removing the microstructure from the second liquid; or drying the microstructure removed from the first treating liquid by exposing same to a liquid vapor having a smaller surface tension than the first treating liquid; or removing the microstructure from the first treating liquid to the atmosphere, and drying the microstructure using an energy beam of high intensity or an ultrasonic wave.

Method of liquid treatment of microstructures comprising bendable structural members

A micro-structure including at least a first bendable member having first and second ends and being supported at the first end only, and either being spaced from a rigid component, or being spaced from a second bendable member also supported only at a first end thereof. The first member has a length L from the first end to the second end specified by one of the following equations: (a) for the first member adjacent to the rigid component: L&lt;(2Edt.sup.3 /3P).sup.1/4, wherein E is a Young's modulus of a material of the first member; d is a distance of the space between the first member and the rigid component; t is a thickness of the first member; and P is an external pressure applied to the first member; or b) for the first member adjacent to the second member: L&lt;(2Ed't.sup.3 /3P).sup.1/4, wherein E, t and P are as defined above; and d' is a distance of the space between the first and second members.

Micro-structures having structural members capable of withstanding

A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).

Semiconductor device

Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic wave. Micro-structures are also disclosed which comprise at least a member liable to be bent but are capable of avoiding permanent deformation of the member resulting from a treatment using a liquid.

Method of liquid treatment of micro-structures comprising structural

Semiconductor device with protective element

An Si or SiC semiconductor layer is subjected to anodic oxidation in an HF solution to form a porous semiconductor layer. Without drying, the porous semiconductor layer is then immersed in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.

Method for manufacturing porous semiconductor light emitting device

An Si or SiC semiconductor layer is subjected to anodic oxidization in an HF solution to form a porous semiconductor layer. Without drying the porous semiconductor layer, it is then dipped in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.

Porous semiconductor light emitting device

A semiconductor device having small diameter via-holes, particularly not greater than 0.6 microns, for a multilayer interconnection is produced by a method comprising covering an interlayer film and via-holes with a continuous, first metal film by a CVD process, and heating and melting by an irradiation of an energy beam a second metal film deposited on the first film by a PVD process, together with the first metal film, to fully fill the via-holes with the material from the outside of the holes, to thus form conductive plugs therein. The deposition of the material of the second metal film and the filling of the via-holes may be simultaneously performed by a high temperature sputtering process.

Method of manufacturing semiconductor devices

A semiconductor photodetector device comprises an insulating gate field effect transistor having a gate in which a PN junction (J) is formed on an insulating layer. The gate is formed of a gate electrode (14) of P.sup.+ -type single crystalline silicon and a gate extension portion (17) of N.sup.+ -type single crystalline silicon. Electric charges generated by a light falling on an area including the PN junction are accummulated in the gate electrode (14). A signal of the accumulated electric charge is amplified by the transistor to obtain an output signal (V.sub.out) for detection.

Semiconductor photodetector device with light responsive PN junction gate

An improved disk exchangeable target mechanism for an ion implantation system includes an effective cooling means for preventing thermal damage to a resist and for improving an implantation quality of semiconductor wafers. The target mechanism includes a metal disk on which a semiconductor wafer(s) to be ion-implanted are mounted on a first face thereof, a support including a metal base having the target disk mounted thereon, and a shaft incorporated with the base, and a medium, provided between a second face of the target disk opposite to the first face and the base, for thermally contact therebetween. Preferably, the base of the support is provided with a cavity and the shaft is provided with holes communicating with the cavity, whereby a cooling medium is inserted into the cavity through one hole and is drained from the cavity through another hole. Furthermore, preferably, the target disk is provided with a thermal transportation unit, such as heat pipes, for transporting thermal energy from a portion(s) at which a high temperature is caused by ion implantation energy, to another portion(s) at which the temperature is low.

Disk exchangeable target mechanism with effective cooling means, for ion

A plasma generating device comprises: a rectangular wave guide for transmitting microwaves, wherein the width of the plasma generating device is decreased in the direction of an electrical field of the microwaves; a plasma generating chamber wherein plasma is generated by absorbing, in a gas, microwave energy transmitted by the rectangular wave guide, and a part of the plasma generating chamber has a rectangular cross-section taken along the plane perpendicular to the microwave propagation direction. A magnetic field generating device is provided having the same axial direction as the direction of propagation of the microwaves and applies a magnetic field having an Electron Cyclotron Resonance intensity to the plasma generating chamber. The magnetic field generating device is provided at least one location outside of the direction of the microwave electrical field direction, and a dielectric window is provided between the rectangular wave guide and the plasma generating chamber to realize a vacuum seal of the plasma generating chamber.

Plasma generating device with stepped waveguide transition

An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through an insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.

Method of manufacturing a non-volatile memory

A dynamic random access memory (DRAM) cell has three MIS transistors arranged in a two-tiered structure with high packing density. A read select MIS transistor has source, drain and channel regions formed in the substrate and is covered by a first insulating layer and a semiconductor layer. A write select MIS transistor has source and drain regions formed in the semiconducting layer, the first insulating layer having a contact window therein through which the drain regions of the write select and read select MIS transistors are connected. A storage MIS transistor has source, channel and drain regions formed in the substrate, the channel region of the storage MIS transistor comprising the source region of the read select MIS transistor and the drain region of the storage MIS transistor comprising the channel region of the read select MIS transistor, the respective channel regions of the read and storage MIS transistors being formed in a common level in the silicon substrate and directly connected therein between the source region of the storage MIS transistor and the drain region of the read select MIS transistor. The write select MIS transistor further may comprise a separate gate electrode, the gate electrodes of the write and read MIS transistors comprising portions of corresponding, separate conducting lines serving as write select and read select lines, respectively.

Two-tiered dynamic random access memory (DRAM) cell

A ROM including memory cells having characteristics corresponding to the '1' or '0' information to be stored, the correspondence to '1' or '0' information being achieved by changing the conductivity type of at least a portion of a semiconductor layer in the semiconductor devices of the memory cells.

Semiconductor device for memory cell

A 1-transistor and 1-capacitor type memory cell includes a first capacitor electrode and a field shield electrode which serves as the second capacitor electrode of the memory cell. A high impurity concentration layer is formed just beneath the first electrode of the capacitor of the memory cell and extends to a field region to form a channel stop area. However, the high impurity concentration layer is inhibited from extending to the transistor gate. This arrangement provides so-called 1-transistor and 1-capacitor type memory cells which are highly integrated, have a long persisting time and are resistant to alpha rays.

Growing community of inventors

Yokohama, Japan

Motoo Nakano