Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Motomu Ukita

Shigeto Maegawa

Tomohisa Wada

Yoshiyuki Ishigaki

Shigenobu Maeda

Toshiaki Iwamatsu

Takashi Ipposhi

Hirotada Kuriyama

Toshiaki Tsutsumi

Toshihiko Hirose

Kazuhito Tsutsumi

Il-Jung Kim

Shigeki Ohbayashi

Yoji Kashihara

Hirotoshi Sato

Tadato Yamagata

Kenji Anami

Kunihiko Kozaru

Eiichi Ishikawa

Yutaka Arita

Hidemoto Tomita

Yoshiyuki Haraguchi

Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (), a channel () and a source () are integrally formed on a surface of a second oxide film () by polysilicon. The drain () is formed to be connected with a pad layer () (second polycrystalline semiconductor layer) through a contact hole () which is formed to reach an upper surface of the pad layer (). The pad layer () positioned on a bottom portion of the contact hole () (opening) is provided with a boron implantation region BR.

Thin-film transistor and method of fabricating the same

A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the first node, and an inverter driving a word line with the power-supply voltage or a ground voltage in accordance with the voltage of the first node. When a corresponding word line is activated, the second node is set at the ground voltage while the first transistor is turned on. In a burn-in test, a burn-in control circuit forcibly turns off the second transistor in a local decoder corresponding to a word line to be activated.

Semiconductor memory device having divided word line structure

The structure around a high-resistance element is formed in mirror symmetry to a plane perpendicular to a semiconductor substrate and the surface of the sheet. Specifically, high-resistance element, contact plugs and extending portion of interconnection layers are symmetric, each of the interconnection layers covering high-resistance element by the same amount. Thus, a semiconductor device of which degree of freedom on designing layout of interconnections which is to be connected to interconnection layers electrically connected to the high-resistance element via contact plugs can be attained.

Semiconductor device

In a test operation for a semiconductor memory device, memory power supply lines are disconnected from a power supply node by using switch gates. Voltages of the memory power supply lines are detected using detection holding circuits. When the detected voltage is lower than a predetermined value, the corresponding memory power supply line is driven to a ground voltage level by the detection holding circuit. Thereby, a standby-current-defective but normally-operable memory cell is forced to an operation-defective state. Then, the standby-current-defective memory cell is identified, and redundancy replacement is performed thereon. Consequently, the standby current abnormality in the semiconductor memory device can be repaired.

Semiconductor memory device and testing method therefor

An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application Of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.

Thin film transistor used in semiconductor memory for achieving reduction in power consumption

A semiconductor memory device includes load circuits of column sense amplifiers arranged correspondingly to Y-addresses (global bit line pairs), respectively. A plurality of memory blocks commonly use the load circuit. Each memory block includes input circuits of the column sense amplifiers for the bit line pairs, respectively. Each input circuit is activated in response to the corresponding block select signal. In response to the potential on the corresponding bit line pair, a potential difference occurs on the corresponding global bit line pair. The load circuit increases this potential difference.

Semiconductor device provided with a circuit performing fast data

An internal voltage generating circuit down-converts an external supply voltage and changes a reduction in its output voltage level from the external supply voltage level as the external supply voltage increases. The internal supply voltage is kept lower than the external supply voltage by the constant value while the external supply voltage stays under a predetermined voltage. The reduction amount is increased in proportion to the external supply voltage while the external supply voltage is over the predetermined voltage.

Internal supply voltage generating circuit for generating internal

A resistor connected in series with a source of external supply potential and a transistor circuit. The transistor circuit comprises a plurality of MOS transistors each of whose drain and gate are connected together, and is grounded. This transistor circuit detects whether an external supply potential is below or above a specific value. When the external supply potential is detected as being below the specific value, another MOS transistor connected to the source of external supply potential is made to conduct, and the external supply potential is supplied to a semiconductor memory circuit without voltage step-down. However, when the external supply potential is detected as being above the specific value, the external supply potential is stepped down through the other MOS transistor, and supplied to the semiconductor memory circuit. An internal supply potential is supplied to a semiconductor memory circuit device in a specific range even if the external supply potential fluctuates.

Semiconductor potential supply device and semiconductor memory apparatus

In a line configuration of each memory cell array employed in a semiconductor memory device, a pair of bit line signal input/output lines or a pair of input/output data lines for transmitting complementary signals are disposed on both sides of and adjacent the global word line so as to cancel the influence of the global word line. By these configurations, the number of shielded lines may be reduced and the width of each line and the interval between the lines are arrayed for preventing the respective lines from breaking or being short-circuited.

Semiconductor memory device having improved wiring architecture

A memory cell includes two bipolar transistors. An upper side word line is connected to the gates of one access transistor and one depletion type transistor in the memory cell. A lower side word line is connected to the gates of the other access transistor and the other depletion type transistor in the memory cell. In data write operation, the potential on the upper side word line is set to 'H' level for a prescribed period and the potential on the lower side word line is thereafter set to 'H' level for a prescribed period, regardless of the type of data. As a result, a circuit related to row decoding can be simplified since a circuit for determining the type of data is not necessary in the circuit related to row decoding.

Static type semiconductor memory device with two word lines for one row

An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.

Semiconductor device with reduced power consumption and thin film

In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.

Semiconductor memory device having two layers of bit lines arranged

A static RAM includes: a memory cell array including word lines, bit line pairs and memory cells; a row recorder; a column decoder; a DTD signal generator responsive to transition of input data or transition of a write enable signal for generating a data transition detection signal for a prescribed time period; and a write driver responsive to the write enable signal and the data transition detection signal for supplying the input data to a bit line pair selected by the column decoder. Even when there is a noise in write enable signal during reading cycle and data transition detection signal is generated erroneously, erroneous writing of data can be prevented, since write enable signal is not supplied to the write driver.

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Hyogo, Japan

Motomu Ukita