Renesas Electronics Corporation

Motoki Kimura

Seiji Mochizuki

Kenichi Iwata

Hiroaki Nakata

Keisuke Matsumoto

Tetsuya Shibayama

Kazushi Akie

Takafumi Yuasa

Fumitaka Izuhara

A video decoding processing apparatus which can reduce overhead for the start of parallel decoding processing. The video decoding processing apparatus includes a parsing unit, and first and second video processing units. A coding bit stream including information of largest coding units each having at least a prescribed pixel size is supplied to an input terminal of the parsing unit. The parsing unit performs parsing of the syntax of the coding bit stream to thereby generate parallel-processable first and second intermediate streams from the largest coding unit. The first and second video processing units parallel-process the first and second intermediate streams generated from the parsing unit.

Parallel video decoding processing apparatus and operating method thereof

The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.

Data processor with a load instruction that branches based on a control register value and a bit or bits read from memory

The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves. Errors are not generated in decoding and the decoded image quality does not deteriorate.

Parallel processing image encoding device with variable length coding

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Kanagawa, Japan

Motoki Kimura