Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Denso Corporation

Hitachi, Ltd.

Renesas Electronics Corporation

Other

Motoki Kanamori

Atsushi Shikata

Kunihiro Katayama

Atsushi Shiraishi

Shigeo Kurakata

Takayuki Tamura

Kenji Kozakai

Shinsuke Asari

Hidefumi Oodate

Kazunori Furusawa

Yosuke Yukawa

Yusuke Jono

Yuusuke Jono

Chiaki Shinagawa

Yasuhiro Nakamura

Tetsuya Iida

Satoshi Yoshida

Ichiro Yoshida

Kiyohiko Sawada

Chiaki Kumahara

Hidefumi Odate

Kazuto Izawa

Hidetaka Tanaka

Kiyohito Narita

Masato Matsumoto

Shingo Takeda

A vehicle control system includes a first electronic control apparatus and a second electronic control apparatus. The first electronic control apparatus includes a first controller, a first communication circuit, and a housing. The first controller is configured to execute a first operating system that operates a first application. The housing is configured to contain the first controller and the first communication circuit. The second electronic control apparatus includes a second controller and a second communication circuit. The second controller is configured to execute a second operating system that operates a second application. The second communication circuit is configured to perform data communication with the first communication circuit.

Vehicle control system

An in-vehicle system includes a primary CPU that is mounted in a vehicle and operates on a general-purpose OS, and a peripheral device that is controlled by the primary CPU. The in-vehicle system further includes a secondary CPU that operates on a real-time OS. The secondary CPU performs an initialization process on the peripheral device at startup, and then assigns control of the peripheral device to the primary CPU.

In-vehicle system

A data processing device includes: a first controller requiring a first activation time; a second controller requiring a second activation time, which is shorter than the first activation time; and a data processor for switching a mode, in which data is processed, between a first processing mode without collaboration with the first controller, and a second processing mode in collaboration with the first controller. The data processor processes data in the first processing mode after completing the activation of the second controller and before completing the activation of the first controller; processes data in the second processing mode after completing the activation of the first controller; and processes data in the first processing mode after a fault occurs in the first controller.

Data processing device

A navigation device for a vehicle includes: a memory device including a NAND type flash memory for storing a predetermined program and a boot program and a controller for searching a failure block in the flash memory and managing a corresponding relation between a logic block and a physical block with eliminating failure blocks; a back-up power source; a power source switch for coupling the memory device with the back-up power source; a power source for generating a predetermined voltage with using the back-up power source; a control device energized from the power source with the predetermined voltage so as to be activated; and a power source control device. The control device determines whether activation is performed for the first time. The control device executes a stand-by process, and then, executes a boot process when the activation is performed for the first time. The control device executes the boot process without executing the stand-by process when the activation is after the first time. The power source control device controls the power source to function when the power source control device receives an activation signal from the power source switch. When the power source switch stops the activation signal, the power source control device stops the operation state of the power source.

Navigation device for vehicle

An in-vehicle apparatus includes: a flash memory; a memory controller for executing an initialization process; a backup power source; a power source; a controller; and a power source controller. According to incompletion of initialization, the controller executes standby/boot process. According to completion of initialization, the controller executes the boot process. According to reception of data backup instruction, the controller stores data in the memory. The power source controller switches to a trigger standby mode. According to trigger, the power source controller inputs the energization instruction to the power source. According to termination of trigger, the power source controller inputs the data backup instruction to the controller. According to completion of backup, the power source controller halts to input the energization instruction, and switches to the trigger standby mode. According to incompletion of backup, the power source controller resets the switch and the power source.

In-vehicle apparatus

A voltage control system is configured with a constant voltage circuit, a semiconductor package and a power supply package. A power supply chip of the power supply package is configured to control the constant voltage circuit based on an input voltage supplied to the semiconductor package and an operating voltage of a semiconductor device so that the input voltage decreases as the voltage difference between the input voltage and the operating voltage increases.

Input voltage control circuit using two differential amplifiers to regulate operating voltage

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data. FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controllerto the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Memory card and its initial setting method

The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

Memory apparatus which provides notification of memory capacity

A controllerof a memory card is a provided with a command decoding circuitfor decoding commands issued by a host HT, a command enable registerin which the validity or invalidity of the received command, and a command detection signal generating circuitfor detecting a valid command on the basis of the result of decoding by the command decoding circuitand a value set by the command enable register. If the command enable registerreceives a validly set command, the command detection signal generating circuitwill supply a detection signal to a control unitto execute processing prescribed for each command. the command enable registerreceives an invalidly set command, no detection signal will be supplied, and the command will be ignored.

Memory card and data rewriting method

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data. FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.

Nonvolatile memory wear leveling by data replacement processing

A memory card () includes an electrically rewritable non-volatile memory (), a data processor () having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit () having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory () for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Nonvolatile semiconductor memory apparatus having buffer memory for storing a program and buffering work data

Memory card apparatus configured to provide notification of memory capacity

When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

Non-volatile semiconductor memory device

The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD card. In a normal MMC mode, the data is outputted at a fall edge of a clock signal. A frequency of the clock signal is about 20 MHz. When the data is outputted at the fall edge of the clock signal, data output is in time for a next clock signal. When a parameter '1' is set to a timing register provided in a host interface, the memory card is transitioned into the HS-MMC mode. In the HS-MMC mode, a clock signal frequency is increased to about 52 MHz. Here, the data is outputted at the rise edge of the clock signal, whereby the data output is brought in time for the rise edge of the next clock signal.

Growing community of inventors

Tachikawa, Japan

Motoki Kanamori