Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Electronics Corporation

Motoki Higashida

Makoto Hatakenaka

Hideo Nagano

Masayuki Koyama

Kikuo Muramatsu

Tomoko Ando

Takahiko Arakawa

Yusuke Matsunaga

Masaru Hagiwara

An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.

Information device including main processing circuit, interface circuit, and microcomputer

An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.

Semiconductor device mounting chip having tracing function

There is disclosed a method for reducing leakage current of an LSI, which enables information not memory-mapped in the address of a CPU to be easily saved, and information saving and returning to be carried out by simple switching operations without needing any special switching operations by the CPU. An LSI chip is divided into two parts, namely a main power supply region and a backup power supply region. A scan path is provided to interconnect memory units including a CPU, a CPU peripheral circuit and so on, in the main power supply region. When an operation standby state is set, a scanning operation through the scan path is started, information held in the memory units of each of the circuits in the main power supply region is read, and then thus read information is saved in an storage section in the backup power supply region.

Method for reducing leakage current of LSI

An electronic apparatus has in a CPU core an instruction correcting circuit that includes memory cells, a comparator and a selector. The memory cells store, when initializing the electronic apparatus, a correction address, a correction instruction and a correction enabling bit, which are associated with contents of a read-only memory. The comparator compares an instruction address output from an instruction prefetch stage of the CPU core with the correction address stored in the memory cells. The selector selects either an instruction code read from the instruction address of the read-only memory or the correction instruction stored in the memory cells in response to a compared result of the comparator. The electronic apparatus can correct the ROM data after manufacturing without reducing the number of available interrupts or the operation speed of the CPU.

Electronic apparatus with ROM data correction function

An LSI with built-in CPU includes a CPU core, an internal CPU bus connected to the CPU core, an external memory access-use external pin for accessing an external memory and a bus selector for outputting signals of the internal CPU bus to the external memory access-use external pin when the external memory is not being accessed.

Integrated circuit with built-in processor and internal bus observing method

A multiplexer is provided for selecting Central Processing Unit (CPU) operation trace information sent from a debug support unit and an internal signal on an internal bus in accordance with a test mode signal, and for transmitting the selected information or signal to a pin terminal for CPU operation trace information signal. A semiconductor integrated circuit device with a processor is provided which allows easy external monitoring of the internal signals, and therefore allows easy debugging even at an on-board level without increase in number of the pin terminals.

Semiconductor integrated circuit device with processor

An in-circuit emulator (ICE) including an internal trace memory and a bit-width converter. The internal trace memory is embedded in an ICE CPU to trace CPU internal signals fed from a CPU core that executes the same operations as a CPU of a debugged system. The bit-width converter converts the CPU internal signal, which is read out of the internal trace memory, into a plurality of reduced bit-width signals, and supplies them to an ICE controller outside the chip of the ICE CPU in multiple cycles. The configuration makes it possible to remove the restriction imposed, by the number of terminals of the ICE CPU chip, on the number of bits of the CPU internal signal to be output in parallel, and to overcome the difficulty involved in sampling the internal CPU signals by the trace memory, even if the operation frequency of the ICE CPU increases.

In-circuit emulator with internal trace memory

A semiconductor integrated circuit (1) has a scan test circuit (6) and a target test circuit (4), connected to a CPU (3) and a RAM (2) through internal buses (5a and 5b) that are mounted on a same semiconductor chip. The scan test circuit (6) provides test signals to the target test circuit (4) having a plurality of flip flops connected one another in a line like a string of beads as a shift register.

Semiconductor integrated circuit with test device

Buffer trees are detected in an inputted logic circuit and sets of driver gates included in the respective buffer trees are made (in Step 102). A set of gates relating to more than one buffer tree, i.e., a group of gates to be optimized, is detected (in Step 103). The groups of gates to be optimized are classified according to the symmetry in logic structure (in Step 104). Each group of gates to be optimized is extracted (in Step 105). The buffer trees are restructured so as to be in a symmetrical relation with each other (In Step 106). Through the above process, the buffer trees are optimized to be in a symmetrical relation of logic structure. Thus, the method of optimizing the logic circuit to ensure reduction in routing area, total length of interconnections and delay of the layout after placement is accomplished.

Growing community of inventors

Tokyo, Japan

Motoki Higashida