Sharp Kabushiki Kaisha Corporation

Motoji Yagura

John Kevin Twynam

Toshiaki Kinosada

Hiroya Sato

Koken Yoshikawa

Toshiyuki Shinozaki

Masanori Kominami

A Heterojunction Bipolar Transistor, HBT, () containing a collector layer (), a base layer () and an emitter layer () is constructed such that the collector layer (), the base layer () and the emitter layer () have different lattice constants of a, aand arespectively, and a value of abetween values of aand a(in other words, the values of a, aand asatisfy a relationship of a&#x3e;a&#x3e;aor a&#x3c;a&#x3c;a). According to the present invention, the HBT having a high reliability can be realized without altering the existing apparatus and steps for producing the HBT extensively.

Heterojunction bipolar transistor having specified lattice constants

A semiconductor device includes: a semiconductor layered structure including a predetermined mesa portion, formed on a semiconductor substrate; a support member formed so as to bury the mesa portion; and an interconnection layer formed on a top surface of the semiconductor layered structure so as to extend over a top surface of the support member. The interconnection layer is in contact with only a top surface of the mesa portion without being in contact with a bottom surface of the mesa portion. The top surface of the support member has a smoothed profile, and the top surface of the mesa portion and the smoothed top surface of the support member are in substantially the same plane.

Semiconductor device and method for fabricating same

An ohmic electrode structure includes an n-In,Ga,As layer where 0<x&lE;1; a Pt or Pd layer provided on the n-In,Ga,As layer; and at least one metal layer provided on the Pt or Pd layer. A semiconductor device includes a substrate; a first semiconductor layer having a p-type conductivity provided on the substrate; a second semiconductor layer having an n-type conductivity provided on the substrate; an ohmic contact layer provided on the first semiconductor layer; a barrier layer provided on the second semiconductor layer; a first electrode provided on the ohmic contact layer; and a second electrode provided on the barrier layer. The ohmic contact layer and the barrier layer are each formed of a material selected from the group consisting of Pt and Pd.

Ohmic electrode structure, semiconductor device including such ohmic electrode structure, and method for producing such semiconductor device

An ohmic electrode structure is produced by developing an In.sub.x Ga.sub.1-x As layer epitaxially on a compound semiconductor (n-Ga As), and providing a barrier layer composed of a tungsten nitride (high melting point metallic nitride) by sputtering. Then, electrode patterning is performed on the top of the tungsten nitride barrier layer by the photo-resist technique. After the process, unnecessary portion of the tungsten nitride barrier layer is removed by the reactive ion etching (RIE). On the top of this a Ti layer, a Pt layer and an Au layer are deposited in layers in that order by the lift-off technique to form a metal layer. Here, molybdenum nitride or titanium nitride may be used in place of tungsten nitride.

Ohmic electrode structure for In.sub.x Ga.sub.1-x As layer

A heterojunction type AlGaAs/GaAs bipolar transistor includes an n-GaAs collector layer, a p.sup.+ -GaAs base layer and an n-Al.sub.x Ga.sub.1-x As emitter layer formed in a stack, and an n-Al.sub.y Ga.sub.1-y As ballast resistance layer formed on the emitter layer. The ballast resistance layer has an Al concentration y in the range of 0&lt;y&lt;0.4, and a resistance higher than that of the emitter layer.

Heterojunction-type bipolar transistor with ballast resistance layer

A hetero-junction bipolar transistor includes: a substrate; a first conductive type collector layer disposed on the substrate; a second conductive type base layer having an external base region; and a first conductive type emitter layer having a bandgap larger than the bandgap of the base layer disposed in this order, wherein the emitter layer includes a first emitter layer, an etching stop layer, and a second emitter layer disposed in this order starting from the substrate side; a base electrode is formed on the etching stop layer or the first emitter layer disposed on the external base region; a region of the first emitter layer on the base layer has a thickness such that the region is substantially depleted at all voltages applied when the transistor is normally operated; the second emitter layer has an electron affinity equal to or smaller than an electron affinity of the first emitter layer; and the etching stop layer has an electron affinity larger than the electron affinity of the first emitter layer, and has a thickness of approximately 3 nm.

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Tenri, Japan

Motoji Yagura