Globalfoundries Inc.

Globalfoundries U.S. Inc.

Motoi Ichihashi

Atsushi Ogino

Deepak K Nayak

Kwan-Yong Lim

Ryan Ryoung-Han Kim

Youngtag Woo

Jia Zeng

Xuelian Zhu

Elizabeth Strehlow

James Mazza

The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

Logic cell layout design for high density transistors

The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

Dual airgap structure

The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (SRAM) cell and a read assist circuit structured to apply a negative voltage to the at least one SRAM cell upon asserting of a wordline of the at least one SRAM cell.

Static random access memory (SRAM) assist circuit

A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

Vertical channel transistor-based semiconductor memory structure

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Sunnyvale, CA, United States of America

Motoi Ichihashi