Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Motoi Ashida

Takashi Terada

Tsuyoshi Koga

Daisuke Okada

Hiroji Ozaki

Tsutomu Okazaki

Yasuo Inoue

Masayuki Yamashita

Kazuhito Tsutsumi

Kiyoyasu Akai

Tomohiro Hosokawa

Yoshikazu Kamitani

Yasuichi Masuda

Eiji Hamasuna

Tadashi Nishimura

Yoshiyuki Ishigaki

Yukio Maki

Ryoji Matsuda

Hideaki Nagaoka

Yasumitsu Murai

Yasuhiro Fujii

Makoto Dei

Yoshiyuki Haraguti

A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.

Semiconductor memory device with memory array and dummy memory array

To provide a magnetic memory device that can suppress the reduction of function of a magnetic memory element, and a manufacturing method thereof. A magnetic memory device includes a magnetic memory element capable of holding data based on a magnetized state thereof, and a digit line and a bit line which are capable of changing the magnetized state of the magnetic memory element by a magnetic field generated. The magnetic memory element is disposed above the digit line and the bit line at an intersection part of the digit line and the bit line. The digit line has a first width at the intersection part, and the bit line has a second width at the intersection part. The first width is larger than a third width of the magnetic memory element, and the second width is smaller than a fourth width of the magnetic memory element.

Magnetic memory device, and manufacturing method thereof

A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.

Semiconductor memory device and manufacturing method thereof

A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Semiconductor device having electrode and manufacturing method thereof

Semiconductor device having a split gate structure with a recessed top face electrode

Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.

Method of manufacturing semiconductor device having dual gate electrode

A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

Semiconductor device and method of manufacturing the same

Semiconductor device

A semiconductor device includes: a semiconductor substrate having two types of active regions that are a PMOS region and an NMOS region separated from each other in plan view by a PN separation film; and a dual-gate electrode extending linearly across the PMOS region, the PN separation film and the NMOS region collectively on an upper side of the semiconductor substrate. The dual-gate electrode includes a P-type portion, an N-type portion and a PN junction positioned therebetween. The PN junction includes a silicide region. The silicide region is apart from both the PMOS region and the NMOS region and formed within the area of the PN separation film in plan view.

An access transistor, provided between a storage node in a memory cell and a bit line is formed of a P channel MOS transistor including P type first and second impurity regions formed in an N type well and a gate electrode. Buried interconnection is formed of metal having high melting point such as tungsten and provided stacked on a driver transistor formed on a main surface of a P type well and the access transistor. A polysilicon film forming a P channel TFT as a load element is formed on the buried interconnection, which is planarized, with an interlayer insulating film interposed.

Semiconductor memory device with static memory cells

A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Semiconductor memory device

Growing community of inventors

Tokyo, Japan

Motoi Ashida