Fujitsu Semiconductor Limited

Motohiro Nakai

Tomohiro Fukuoka

An image processing apparatus includes a decoding processor including a decoder configured to decode encoded data of image data of one frame having a plurality of pixels encoded by a variable length coding method and generating decoded data, and a data transfer unit configured to select decoded data in a target partial region in which a predetermined image processing is to be performed as partial image data out of the decoded data inputted from the decoder and transfer the selected data; and an image processor configured to perform the given image processing on the partial image data selected in the data transfer unit and store the image-processed partial image data in a storage device.

Image processing apparatus, imaging apparatus, and image processing method

An image processing device for use with a storage circuit processes image data for a frame formed by a plurality of pixels. The image processing device includes a first functional macro performing first image processing on the image data, generating first processed image data, and temporarily storing the first processed image in a predetermined region of the storage circuit. A second functional macro performs second image processing following the first image processing. The second functional macro reads the first processed image data from the predetermined region of the storage circuit, performs the second image processing on the first processed image data, and generates second processed image data. A monitor circuit, arranged in the first or second functional macro, monitors a frame processed by the other one of the functional macros and a number of a data line in the frame that is being processed.

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Kasugai, Japan

Motohiro Nakai