Kabushiki Kaisha Toshiba

Motohiro Enkaku

Takehiko Hojo

Toshiya Kato

Kenichiro Mimoto

A semiconductor integrated circuit device includes a programmable circuit in which information is programmed, an information holding circuit which electrically holds information programmed in the programmable circuit, a compression circuit which compresses information held in the information holding circuit, an information output circuit which outputs expected value information, and a detection circuit which checks whether information held in the information holding circuit is destroyed or not. The detecting circuit compares expected value information of the information output circuit with compression information of the information compression circuit to check destruction of information held in the information holding circuit.

Semiconductor integrated circuit device and error detecting method therefor

An I/O circuit is capable of achieving a reduction of power consumption by preventing leak current while performing the pull-down or pull-up operation. The I/O circuit of the present invention is constructed so that an I/O terminal 5 is pulled down or pulled up only when the I/O terminal 5 is in an open state or at the same potential as the pull-down or pull-up potential provided to the I/O terminal 5 when the high impedance state is input to the I/O terminal 5. The I/O circuit comprises an output circuit providing tri-state outputs, a switch circuit for the pull-up or pull-down operation, and an input circuit connected to the I/O terminal, the switch circuit and internal circuits of a device.

Input/output circuit and a method for controlling an input/output signal

In a first inter-layer insulator film above source/drain regions of basic cells constituting a gate array, first contact holes (joint contacts) are placed, so that wings (joint plates) electrically connected with the source/drain regions via plugs in those joint contacts is locally placed above the source/drain regions. Above the wings is formed a second inter-layer insulator film, above which is formed a first level interconnection which constitutes one of metal wiring layers. In the second inter-layer insulator film are formed second contact holes, so that a semi-custom ASIC is provided in which the wings and the first level interconnection are electrically interconnected via the plugs in those second contact holes. The first and second contact holes, first level interconnection, etc. are automatically designed by use of a computer based on a grid pattern in the basic cells. According to the present invention, the basic cells need not be re-designed even if a first pitch of a pattern of the first contact holes is different from a second pitch of a pattern of the second contact holes, thus easily enabling automatic customization. Without increasing the area of the source/drain regions in the basic cells, any pitch of the wiring layers can be selected, thus increasing the integration density without deteriorating the performance of MOS FETs at the same time as reducing time required for the customization.

Contact holes of a different pitch in an application specific integrated

A semiconductor integrated circuit device of multi-layer interconnection structure includes a pad formed of a multilayer interconnection layer. The power source pad is connected to a power source interconnection layer via a lead-out interconnection layer which is formed of the same multilayer interconnection layer as that used to form the power source pad.

Semiconductor integrated circuit device of multilayer interconnection

A semiconductor device includes a circuit block formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto, a first current path pattern formed in a first layer of the multilayered wiring layers and running around the circuit block, a second current path pattern formed in a second layer of the multilayered wiring layers and running around the circuit block, part of the second current path pattern lying over the first current path pattern and the other portion of the second current path pattern lying off the first current path pattern so as to define a connection space with a predetermined width between the first current path pattern and the second current path pattern, a first signal path pattern formed in the first layer of the multilayered wiring layers and serving as a signal path to the circuit block, a second signal path pattern formed in the second layer of the multilayered wiring layers and serving as the signal path to the circuit block, and a via contact, formed in the connection space, for electrically coupling the first signal path pattern and the second signal path pattern.

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Sagamihara, Japan

Motohiro Enkaku