Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Motohide Nishibata

Fumio Sumi

Yoshiyuki Iwamura

Shuichi Takayama

Kunihiko Hayashi

Tsutomu Mikami

Junko Sayama

Atsushi Ubukata

Takio Yamashita

Kouichirou Miyawaki

Shoji Nagata

Yuki Kitamura

The inter-module communication apparatus includes a first module and a second module which operate individually on a processor; a common memory interposed between the first module and the second module for functioning as a communication medium; a plurality of communication paths provided to the common memory for connecting the first module and the second module to be communicable; a transmission unit for transmitting communication data from the first module to the second module; a reception unit for receiving the communication data transmitted from the first module by the second module; a processing order relating device for registering a processing order of communication processing, which is set between each communication path constituting a plurality of the communication paths; and a processing order relevance register which, for transmission, registers the processing order to the processing order relating device when the processing order is set for the communication data to be transmitted.

Inter-module communication apparatus

A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.

Semiconductor integrated circuit device and debugger device for the same

A debugging apparatus is disclosed which verifies a program to be embedded into a target machine by running the program in an environment which is one or the target machine, an emulator, and a simulator. Each environment includes operation state information of the program and inputs and outputs the operation state information in a form unique to the environment. The debugging apparatus includes; target environment storing unit for storing an identification name of the target environment; receiving unit for receiving a command from an operator; instruction detecting unit for detecting a certain instruction in the command; specifying unit for, when the certain instruction is detected, specifying a target environment specified by the identification name as a source target environment and for specifying any of the rest of the environments as a destination target environment; reading unit for reading operation state information from the source target environment; converting unit for converting the operation state information into operation state information written in a form unique to the destination target environment; setting unit for setting the converted operation state information in the destination target environment; and operation resuming unit for resuming the operation of the program in the destination target environment.

Debugging apparatus for debugging a program by changing hardware

A program development system in which the debugging apparatus is informed of all of the optimization processes which have been performed. A primitive storage unit stores record information for the optimization processes. The input unit receives an input of a variable and a value, or an input of a line where execution is to be halted. The primitive combining unit obtains record information showing the optimization processes. The code execution unit executes the execution code. The variable operation unit obtains the value of a variable based on relations between variables and resources. The output unit displays the obtained value of the variable. The line display unit displays the program or the generated execution code. The line information display unit displays, in line units, information relating to the optimization performed for each line, The operation-possible variable display unit displays, for each line, variables which can be set and referred to in the line. The optimization process display unit shows how the optimization affects each variable.

Debugging information generation system

Growing community of inventors

Wakayama, Japan

Motohide Nishibata