Xerox Corporation

Mostafa R Yazdy

Harry Jonathan McIntyre

Alan J Werner, Jr

Mehrdad Zomorrodi

Lamar T Baker

Steven A Buhler

Abdul M ElHatem

Jaime Lerma

Scott Alan Elrod

Babur B Hadimioglu

Guillermo Lao

Mohamad M Mojaradi

Dale Sumida

Methods and apparatus for optimizing the phase lock loop circuitry of sub-pixel clock generators for situations where frequent switching between different system printing speeds, and hence clock frequencies are required. An optimizing circuit is associated with a sub-pixel clock generator for clamping an input voltage to a voltage controlled oscillator controlling clock frequency between a desired range. The clamping circuitry comprises a comparator for detecting when the voltage has moved out of the desired range and then charges or discharges a loop filter circuit controlling the input voltage to the VCO to keep the input voltage within the desired range.

Sub-pixel generation for high speed color laser printers using a clamping technique for PLL (phase locked loop) circuitry

Methods and apparatus for optimizing the phase lock loop circuitry of sub-pixel clock generators for situations where frequent switching between different system printing speeds, and hence clock frequencies are required. A timing control logic circuitry is associated with the sub-pixel clock generator for a graduated change in charge pump current. The timing control logic circuitry comprises a plurality of current generators serially connected with the charge pump current via associated switches for the selective adjustment of charge pump current in a graduated manner.

Gradual charge pump technique for optimizing phase locked loop (PLL) function in sub-pixel generation for high speed laser printers switching between different speeds

Data-processing systems and methods include a rendering device which renders documents based upon the timing and duration of a laser beam associated with particular pixel data. Additionally, a controlling mechanism for controlling and adjusting the particular pixel data can be provided, wherein the controlling mechanism is subject to pixel clock signal in order to optimize a performance of the rendering device under varying rendering parameters and thereby enhance the quality of data rendered via the rendering device. Such a controlling mechanism can be implemented as a programmable phase locked loop circuit to which a pixel clock signal and a frequency are applied in order to provide at least one output signal for controlling the laser beam.

Systems and methods for setting configuring rendering parameters for high-speed rendering devices

An improved ROS driver circuit for an electrophotographic printing system includes a sub-pixel clock generator, a parallel to serial converter, and a raster output scanner (ROS) light source. The sub-pixel clock generator generates a sub-pixel clock signal that has a period less than a period of a video data clock and this clock signal is used by the parallel to serial converter to convert a parallel video data stream into a serial video data bit stream. The serial video data bit stream modulates the ROS light source to provide sub-pixel control of the light signal generated by the ROS light source.

Method and system for improved raster output scan control in an electrophotographic system

Circuit architecture for driving piezoelectric transducers with a Head Drive ASIC powered with only regular (constant) power supplies (instead of ramped and shaped power supplies) is disclosed. The circuit architecture consists of current mirroring systems and current switching techniques used to generate the required particular voltage waveforms across the capacitive transducers using only constant (DC) power supplies. There is no need for high voltage switching elements in this approach.

Current switching architecture for head driver of solid ink jet print heads

Circuitry for providing a method (semi-analog) for normalization procedure of the Head Driver ASIC is disclosed. The circuitry utilizes current DAC's (Digital-to-Analog Converts) to adjust the amplitudes of the voltages across piezoelectric elements, based on predetermined normalization (calibration) data which are stored in separate latches (a different normalization data for each individual transducer). The transducers all receive their respective calibrated voltage values all at the same time by varying the current slope delivered to each. This method provides more simplicity and more accuracy for normalization procedure and results in better performance then using digital circuitry and digital counters.

Normalization of head driver current for solid ink jet printhead

Circuitry for providing a method (semi-analog) for normalization procedure of the Head Driver ASIC is disclosed. The circuitry utilizes current DAC's (Digital-to-Analog Converts) to adjust the amplitudes of the voltages across piezoelectric elements, based on predetermined normalization (calibration) data which are stored in separate latches (a different normalization data for each individual transducer). The transducers all receive their respective calibrated voltage values all at the same time utilizing a single current slope delivered to each. This method provides more simplicity and more accuracy for normalization procedure and results in better performance then using digital circuitry and digital counters.

Normalization of head driver current for solid ink jet printhead by current slop adjustment

An electronic driver circuitry for an RF switch diode used in Acoustic Ink Jet Printing (AIP) systems is disclosed The electronic driver circuitry consists of a PMOS transistor and a poly resistor used to control the on/off states of the RF switch diode wherein the drive current for the RF switch diode is the same as the current in the PMOS transistor. To compensate for undesirable variations in the RF switch diode, the driver circuitry is designed such that the current in the PMOS transistor is adjusted in an opposite direction to cancel the unwanted variations.

Process insensitive electronic driver circuitry for integrated RF switching diodes

An electronic driver circuitry for an RF switch diode D used in Acoustic Ink Jet Printing (AIP) systems that compensates and cancels out undesired variations and non-idealities is disclosed. The electronic driver circuitry consists of a second RF switch diode D used as a compensation diode that is placed in close physical proximity to the RF switch diode D used for RF switching. To compensate for undesirable variations in the RF switch diode D , the driver circuitry is designed such that the current in the RF switch diode D is adjusted in an opposite direction to cancel the unwanted variations of the RF switch diode D

Process and temperature compensation circuit for integrated RF switching

Described are various compensation circuit designs to ensure proper shutoff of an unselected transducer in a transducer switching matrix. The switch of an unselected transducer is moved to a strong OFF state by injection of a compensation current. The compensation network is implemented as semiconductor integrated circuits which provide a high-voltage column switching diode, and a compensation switch. The compensation switch and column switching diode are configured such that they are isolated from each other.

Printhead array compensation device designs

An acoustic inkjet printhead utilizes a pulse width modulation to control droplet size or ejection velocity. An individual control pulse controls the duration and the time a RF signal is applied to each transducer. To modify the RF signal of each transducer, the pulse width of each control signal can be modified according to a predetermined correction data. The rising edge of the control data is delayed according to the correction data while the falling edge is kept the same.

Pulse width modulation for correcting non-uniformity of acoustic inkjet printhead

A pulse width modulation circuit utilizes a clock divider to generate a plurality of clocks to be used by a plurality of delay blocks. Each delay block has plurality of delay elements each of which receives one the plurality of clocks. Each delay block receives a delay data, selects a number of the plurality of clocks based on the delay data and activates the respective delay elements for delaying its input signal.

Pulse width modulation circuit

There is disclosed a shunt voltage regulator which utilizes a reference voltage which generates a floating output voltage with respect to a voltage to be regulated. The shunt voltage regulator of this invention also utilizes the voltage to be regulated as a power supply to its reference voltage generator, the level shifters and the Op-Amp.

Shunt voltage regulator utilizing a floating reference voltage

There is disclosed a converter for converting a floating voltage of a Band Gap Reference voltage generator fabricated in P-substrate CMOS technology to a fixed voltage with respect to ground. The converter of this invention utilizes a subtractor to convert the floating voltage to a fixed reference voltage. In addition, the converter of this invention utilizes two level shifters which are able to level shift the floating voltage down and level shift the shifted down voltage substantially back to the level of the floating voltage in order to allow a buffer to be used prior to the subtractor.

Design technique for converting a floating band-gap reference voltage to

An infrared reflectance densitometer (IRD) sensor which utilizes four blocks each of which generates an element of a given equation and a fifth block which generates an output voltage based on the given equation. The IRD sensor eliminates a problem known as hunting.

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Los Angeles, CA, United States of America

Mostafa R Yazdy