Vlsi Technology, Inc.

Mossaddeq Mahmood

Balmukund K Sharma

Arnold Ginetti

Christopher H Kingsley

Francois Silve

Nels B Vander Zanden

Mandalagiri Chandrasekhar

A method and apparatus for designing circuits uses parameterized Hardware Description Language (HDL) modules stored in a library. A datapath synthesizer accesses the library and assigns values to parameters to form specific implementations of the parameterized HDL modules. The specific implementations of the parameterized HDL modules are used by the datapath synthesizer to implement an HDL circuit description. Each parameterized HDL module includes an entity description, a behavioral description, and an implementation description

Apparatus and method for synthesizing integrated circuits using

A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected parameter, such as circuit timing, circuit power consumption, or circuit area. Relying upon the set of cell instance performance values, a problematic component within the circuit is identified for replacement. A set of functionally equivalent candidate components are then identified. Each candidate component is analyzed with respect to the selected parameter. The analysis identifies an optimally performing candidate component. An instance of the optimally performing candidate component is then substituted into the netlist for the problematic component to improve the performance of the circuit.

Method for improving the operation of a circuit through iterative

A method and apparatus for characterizing the timing behavior of datapath in integrated circuit design and fabrication. A set of circuit specifications for an integrated circuit are developed and described in a hardware description language (HDL) description. A datapath library including datapath cells and a gate library including primitive gate cells are provided, and a netlist is synthesized from the HDL description. The netlist is composed of datapath cells from the datapath library and primitive gate cells from the gate library. If a datapath cell instance in the netlist does not meet the timing constraints imposed by a user for the circuit, an alternative datapath cell instance can be substituted for that cell instance in a resynthesis and optimization step. An integrated circuit is preferably fabricated as specified by the resynthesized netlist. The netlist is preferably resynthesized multiple times in an iterative loop to optimize the netlist according to the constraints. The timing information for alternative cells used in the resynthesis of the netlist can be retrieved from a timing database in one embodiment. Timing information for datapath cells is stored in the timing database in a pre-characterization process, and the location of the timing information in the timing database is stored in a query database. In another embodiment, timing information for alternative datapath cells is calculated dynamically during the resynthesis process for optimizing the timing of a netlist.

Method and apparatus for characterizing timing behavior of datapaths for

A set of circuit specifications including an internal memory structure is developed and then described in a hardware description language that is entered into a computer system. The circuit description is then synthesized on the computer to form a netlist to specify the circuit. From this netlist, an integrated circuit is produced on a semiconductor die, which is then packaged for use. A method for synthesizing a netlist from a hardware description including an internal memory structure includes converting the hardware description into an internal signal list, which contains an indication of the presence of an internal memory structure in the described circuit. For each memory structure indicated, synthesis is performed using a memory cell library, and compatibility between the hardware description for the circuit and the internal memory structure specified is determined. When compatibility is found, the internal memory structure is instantiated into the netlist for the circuit. A central processing unit (CPU) is connected to a keyboard used to input a hardware description of a circuit. Further included is a hardware description processor implemented on the CPU that creates mask generation data for use with a mask generator to form an integrated circuit. An internal memory structure as described in the hardware description of the circuit is thereby included in the circuit.

Method and apparatus for forming an integrated circuit including a

A datapath circuit synthesizer converts an HDL circuit specification into a circuit netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic and control logic. The control logic is implemented in standard cells or gate arrays using a logic synthesizer. The datapath logic is optimally synthesized using a datapath synthesizer having a library of datapath elements, including both structural components and computational components, where some of the computational components are complex circuits having multiple, parallel outputs. Each computational component has associated therewith a set of one or more datapath expressions performed thereby. The received HDL circuit specification is converted into circuit data structures representing the circuit's datapath expressions and structural components. The datapath synthesizer locates all datapath elements in said library matching each such datapath expression and structural component. Then an optimizer determines which datapath expressions can be 'combined', or performed by a single library element, so as to reduce the circuit layout area used. The optimizer can combine multiple datapath expressions so as to use datapath circuit elements having multiple parallel outputs. Finally, one library element is selected for each datapath expression, or combined expression, on the basis of circuit area, speed, power or other optimization criteria. Then the connections between the selected circuit components are computed and the resulting circuit is output in the form of a circuit netlist.

Datapath synthesis method and apparatus utilizing a structured cell

A method for fabricating an integrated circuit includes the steps of: (a) developing a set of circuit specifications for an integrated circuit; (b) encoding the set of circuit specifications in a hardware description language (HDL); (c) synthesizing a netlist including a sequential datapath with a datapath synthesizer from the HDL; and (d) fabricating an integrated circuit as specified by the netlist. A method for datapath synthesis includes the steps of: (a) providing a datapath library including sequential components and combinational components; (b) developing a set of circuit specifications for an integrated circuit; (c) encoding the set of circuit specifications in a HDL; (d) developing a number of IC expression trees derived from the HDL; (e) matching the IC expression trees with library expression trees derived from the datapath library to provide a map of matches; and (f) synthesizing according to the map to create a datapath netlist including both sequential datapaths and combinational datapaths. A datapath synthesizer includes a digital processor, memory coupled to the digital processor, and a datapath library stored in the memory. An input device is used to input a HDL description of circuit specifications into memory, and an IC expression generator develops a number of IC expression trees from the HDL. A matcher compares the plurality of IC expression trees with library expression trees derived from the datapath library to provide a map of matches, and a synthesizer provides a netlist including both sequential datapaths and combinational datapaths according to the map.

Method and apparatus for synthesizing datapaths for integrated circuit

A computer aided design system and method for automatically modifying a specified Hardware Description Language (HDL) characterization of a circuit to reduce signal delays on critical paths of the circuit is described. The specified circuit is analyzed with a logic synthesizer including a novel cell-based timing verifier that determines if a circuit meets specified timing requirements. Timing requirements are tested by computing a slack value for each node of the circuit at the component (macrocell) level, where the slack value represents the difference between the required arrival time of a signal at each circuit node and the computed worst case signal arrival time for the node. The output node having the most negative slack value is identified as a critical node. The HDL description of the circuit corresponding to the critical node is modified with a synthesis directive to substitute the original datapath cell with a better cell in order to improve the circuit's timing performance. The revised HDL description of the circuit is then re-synthesized. Improvements to the circuit may be repeated in this fashion until the circuit meets all timing constraints.

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Mossaddeq Mahmood