Cisco Technology, Inc.

Other

Moshe Voloshin

Rami Zemach

Mark D Cavaro

John H W Bettink

William Norman Eatherton

Vitaly Sukonik

Michael Brian Galles

John Joseph Williams, Jr

Doron Shoham

Michael Laor

Alon Ratinsky

Sarig Livne

John J Williams

John H Bettink

Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for matching items with resources, such as, but not limited to packet processing contexts, output links, memory, storage, specialized hardware or software, compute cycles, or any other entity. One implementation includes means for maintaining distribution groups of items, means for maintaining differently aged resources queues, and means for matching resources identified as being at the head of the plurality of differently aged resources queues and as being primarily and secondarily associated with said distribution groups based on a set of predetermined criteria. For example, even though processing contexts can be shared among different distribution groups of packets, by giving preference to assigning recently used processing contexts for processing packets of a same distribution group, it is more likely that the processing instructions are already in the memory of this processing context, and therefore, processing will not be delayed until such instructions are retrieved into memory.

Assigning resources to items such as processing contexts for processing packets

Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques. In one implementation, a descriptor used in a prior DMA request is modified and then used in a second DMA request.

Methods and apparatus for processing packets including accessing one or more resources shared among processing engines

Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, a packet of multiple streams of packets is received. A subset of bytes of the packet are distributed to the next packet processor determined based on a distribution pattern. The subset of the packet is processed to generate a modified subset, which is gathered in turn based on the distribution pattern; and a modified packet including the modified subset is forwarded.

Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing engines

A method of automatically activating a clock master circuit in a stack of repeaters includes selectively connecting a first on pin in a first repeater to a voltage source when the first repeater is powered on. The first on pin is connected to a power state output pin in a second repeater, wherein the power state output pin is configured to be connected to ground when the second repeater is powered on. A clock master circuit is enabled based on the voltage on the first on pin.

Method and apparatus for automatic activation of a clock master on a stackable repeater

Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.

Synchronous stack bus for fast Ethernet repeater

Synchronous stack bus for fast ethernet repeater

An automatically activated bus termination circuit in a repeater that is suitable for inclusion in a repeater stack including an end unit determination circuit is described. The end unit determination circuit includes a local input connector having an input sense pin. The input sense pin is configured to be connected to an input sense potential when the local input connector is connected to a remote output connector. A local output connector has an output sense pin. The output sense pin is configured to be connected to an output sense potential when the local output connector is connected to a remote input connector. A bus termination circuit is configured to be active when either the input sense pin is not connected to the input sense potential or the output sense pin is not connected to the output sense potential. As a result, the bus termination circuit is activated when a stack bus connection cable is not connected from the local output connector to a remote input connector or when a stack bus connection cable is not connected from the local input connector to a remote output connector.

Method and apparatus for automatic activation of bus termination on a fast ethernet repeater stack

Provided is a system which automatically determines and assigns an appropriate address for each chip in repeater system. All the ASICs in a system are chained together on a serial data ring for address allocation purposes. A &ldquo;First On&rdquo; ASIC in a system initializes the chip address map, assigns itself the first address. The First On ASIC then updates the address map by setting the next address and sends it down the chain to the next ASIC in the system. The second ASIC allocates the incoming address to itself, sets the address for the next ASIC, and passes the address signal on. The process repeats itself until the last ASIC in the chain has an address allocated. The last ASIC the notifies the First On ASIC of its address to close the loop.

Chip address allocation through a serial data ring on a stackable repeater

Provided is a system which automatically determines and assigns an appropriate address for each chip in a repeater system. All the ASICs in a system are chained together on a serial data ring for address allocation purposes. A 'First On' ASIC in a system initializes the chip address map, and assigns itself the first address. The First On ASIC then updates the address map by setting the next address and sends it down the chain to the next ASIC in the system. The second ASIC allocates the incoming address to itself, sets the address for the next ASIC, and passes the address signal on. The process repeats itself until the last ASIC in the chain has an address allocated. The last ASIC then notifies the First On ASIC of its address to close the loop.

Chip address allocation through a serial data ring on a stackable

An apparatus for automatically activating a clock master circuit in a stack of Fast Ethernet repeaters includes a first stackable Fast Ethernet repeater is disclosed. The first stackable Fast Ethernet repeater includes a first on pin having a first on pin logical state. The first on pin logical state is indicative of whether or not the first stackable Fast Ethernet repeater is configured in the stack of Fast Ethernet repeaters so that no other Fast Ethernet repeater occupying a position in the Fast Ethernet repeater stack that is before the position of the first Fast Ethernet repeater is powered on. A weak pull up voltage source is connected to the first on pin. The weak pull up voltage is derived from a switched power supply in the Fast Ethernet repeater so that when the Fast Ethernet repeater is powered on, the weak pull up voltage is present and when the Fast Ethernet repeater is powered off, the weak pull up voltage is not present. A clock master circuit has an enable input that is controlled by the first on pin logical state. A second stackable Fast Ethernet repeater includes a power state output pin. The power state output pin is configured to be connected to ground when the second Fast Ethernet repeater is powered on. A connector cable runs from the first Fast Ethernet repeater to the second Fast Ethernet repeater. The connector cable connects the first on pin from the first stackable Fast Ethernet Repeater to the power state output pin of the second stackable Fast Ethernet repeater. Thus, the clock master circuit in the first stackable Fast Ethernet Repeater is enabled based on whether the second stackable Fast Ethernet repeater is powered on.

Method and apparatus for automatic activation of a clock master on a

An automatically activated bus termination circuit in a repeater which is suitable for inclusion in a repeater stack including an end unit determination circuit. The end unit determination circuit includes a local input connector having an input sense pin. The input sense pin is configured to be connected to an input sense potential when the local input connector is connected to a remote output connector having an output sense pin. The output sense pin is configured to be connected to an output sense potential when the local output connector is connected to a remote input connector. The bus termination circuit is configured to be active when either the input sense pin is not connected to the input sense potential or the output sense pin is not connected to the output sense potential. As a result, the bus termination circuit is activated when a stack bus connection cable is not connected from the local output connector to a remote input connector or when a stack bus connection cable is not connected from the local input connector to a remote output connector.

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Sunnyvale, CA, United States of America

Moshe Voloshin